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sunil_vnit
Observer
Observer
10,348 Views
Registered: ‎10-28-2013

timing constraint problem

hello,

           while synthesizing my code i got some TIMING CONSTRAINT problem.i dont know how to overcome this problem.Is this error create any problem while i will dump this code in FPGA.plz give me any suggestion how to overcome this problem.

 

i have attach my synthesis summary also

-Sunil
Untitled.png
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4 Replies
sahana.barike
Visitor
Visitor
10,345 Views
Registered: ‎07-30-2013

Hi,

Reduce the frequency of the clock you are using for your design..

Regards,
Sahana
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sunil_vnit
Observer
Observer
10,343 Views
Registered: ‎10-28-2013

i did not gave any clock frequency.simply  iahave written the code in xilinx ise 14.v and given a specified fpga board and synthesizing it.but still it gives time constarint problem.

-Sunil
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bassman59
Historian
Historian
10,327 Views
Registered: ‎02-25-2008


@sunil_vnit wrote:

i did not gave any clock frequency.simply  iahave written the code in xilinx ise 14.v and given a specified fpga board and synthesizing it.but still it gives time constarint problem.


You need to set valid timing constraints for your design. This is FPGA 101 basic stuff.

----------------------------Yes, I do this for a living.
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htsvn
Xilinx Employee
Xilinx Employee
9,753 Views
Registered: ‎08-02-2007

 

 

Hi,

 

As 

 

 

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