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Explorer
Explorer
6,788 Views
Registered: ‎01-15-2008

timing constraints in pcf file

Hi,

I have a design I previously compiled in 9.2, and now recompiled in 10.1, and I've had some timing problems with the recent compile.  In tracking this down, I notice some timing constraints in the old (9.2) pcf file that are not present in the new pcf file.  These constraints were apparently generated by mapper, as they don't appear in my source HDL anywhere.  Can anyone school me on where such constraints came from, and why they're not there anymore? 

Thanks,

Rick 

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3 Replies
Xilinx Employee
Xilinx Employee
6,335 Views
Registered: ‎08-10-2007

Re: timing constraints in pcf file

Can you give some examples of the constraints that you're not seeing in 10.1 that were there in 9.2?  Are you getting timing errors now?
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Explorer
Explorer
6,326 Views
Registered: ‎01-15-2008

Re: timing constraints in pcf file

There was a whole bunch like:

TS_OFEBs_OFEB3_ADC_AdcToplevel_I_AdcClock_IntDclkDcmDvBufg_2 = PERIOD TIMEGRP

        "OFEBs_OFEB3_ADC_AdcToplevel_I_AdcClock_IntDclkDcmDvBufg_2"

        TS_lclk_p_3_ * 6 PHASE -3.984 ns HIGH 50%;

It was a month ago, and I think I finally got rid of them by either deleting the pcf, or running "cleanup" on the project, I can't remember which.  But I'd still be interested in understanding where they came from.

Thanks!

 

Rick 

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Xilinx Employee
Xilinx Employee
6,319 Views
Registered: ‎08-10-2007

Re: timing constraints in pcf file

Well constraints that get into the PCF will have originated from a couple of places.  Obviously the UCF and any constraints that are in the HDL.  Also some IP cores from Coregen or EDK will have constraints in their netlists and will add these constraints to the PCF.  Finally, the tools can automatically generate constraints for clocks going through DCMs and PLLs, i.e. if you constrain the input clock the tools will automatically create a constraint for the output clock.  This could be what was happening here.  This doesn't explain why they were in the 9.2i design and not the 10.1 design unless you changed or removed a DCM, PLL or an IP core.
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