02-25-2009 08:48 AM
I have a design I previously compiled in 9.2, and now recompiled in 10.1, and I've had some timing problems with the recent compile. In tracking this down, I notice some timing constraints in the old (9.2) pcf file that are not present in the new pcf file. These constraints were apparently generated by mapper, as they don't appear in my source HDL anywhere. Can anyone school me on where such constraints came from, and why they're not there anymore?
03-26-2009 10:49 AM
03-26-2009 10:10 PM
There was a whole bunch like:
TS_OFEBs_OFEB3_ADC_AdcToplevel_I_AdcClock_IntDclkDcmDvBufg_2 = PERIOD TIMEGRP
TS_lclk_p_3_ * 6 PHASE -3.984 ns HIGH 50%;
It was a month ago, and I think I finally got rid of them by either deleting the pcf, or running "cleanup" on the project, I can't remember which. But I'd still be interested in understanding where they came from.
03-27-2009 02:27 AM