05-05-2019 09:41 PM
When i try to generate bitstream, the bitstream is succesfully generated giving a timing failed warning. can someone suggest how to work around it? The timing summary is as given below.
05-06-2019 11:54 PM
Simple answer: Try different Implementation strategies.
If this does not help, you need to look into the timing path details (go to the "Intra-Clock Paths" category with a red dot in the timing report and check the timing paths details) and analyze why the timing fails on those paths. Based on different issues that result in bad timing, there are different solutions.
You can refer to UG949 for different timing issues and the corresponding solutions.
05-07-2019 01:55 AM
You may also refer to the Xilinx Timing Closure User Guide, UG612.
It will clear up your fundamentals on timing closure.
05-07-2019 02:24 AM
what the tools are trying to tell, is that you code will not work, and if I remember, it will not make a bit file for you .
You need to look at the timing rpeorts and the implimentatoin, see if your code has made what you expected it to, and where you can speed things up,
having said that, the number one cause I see, is people have more than one clock and clock interactoins they did not realise,
and the tools are trying to meet all the timming requirments, including those that are not relavent.
look in the cross clock report,