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adhouib
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Registered: ‎02-06-2017

timing report:finding the design frequency

Hello ,

I created a simple design 4 bit counter using a PLL to increase the input clock frequency from 27Mhz to 391Mhz to clock the counter.

In the ucf file i created a constraint for the input period (input Frequency=27Mhz => period=37.037ns)

I would like to know How can i caluclate the design frequency  or where could i find this information? 

 

1/ When seeing the PAR report i seen a Direct and Derivative Paths. how can i interpret these values?

2/ I launched the TRCE tool and i checked the report gnerated.At the end of this report i  get this information:

Design statistics:
Minimum period: 10.000ns{1} (Maximum frequency: 100.000MHz)

 

I would like to know whether  the mximal frequency value is right and how does it calculated ? 

 

please have a look to the screenshot attached that presents the hdl,the ucf file, the trce report and PAR report

 

please note that i used ISE14.17 and spartan6 X45 family

 

Thank you.

 

Best Regards,

 

 

counter.png
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graces
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Registered: ‎07-16-2008

For question 1, please have a look at these ARs.

https://www.xilinx.com/support/answers/34299.html

https://www.xilinx.com/support/answers/55748.html

 

For question 2, the minimum period is the minimum achievable period from any synchronous paths. If you have multiple clock domains, the more meaningful statistics are the slack for each type of constraints.

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