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hrmt
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Registered: ‎06-09-2018

timing requirement not meet

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Hi guys,

 

when timing requirement not meet in vivado , what should i do?

for example my input delay constraint not meet, what should i do?

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tsjorgensen
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Registered: ‎09-13-2011

If an input delay constraint is not met you have the option to use an MMCM to place the sampling clock edge at a different place in time. By adjusting the phase relationship you can provide more hold time or more setup time whichever is the problem.

A further option is to use an idelay or anything else that can skew your input compared to the clock sampling point in the right direction.

 

Br tsjorgensen

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dpaul24
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Registered: ‎08-07-2014

@hrmt,

 

You have to use the set_input_delay constraint.

Refer to the docu UG903 for details of its usage.

------------FPGA enthusiast------------
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yashp
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Registered: ‎01-16-2013
Hi,

To understand the root cause why timing is not met please share your timing report and schematic for input interface.

Thanks,
Yash
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tsjorgensen
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Registered: ‎09-13-2011

If an input delay constraint is not met you have the option to use an MMCM to place the sampling clock edge at a different place in time. By adjusting the phase relationship you can provide more hold time or more setup time whichever is the problem.

A further option is to use an idelay or anything else that can skew your input compared to the clock sampling point in the right direction.

 

Br tsjorgensen

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hrmt
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Registered: ‎06-09-2018

your suggestions was very useful.

thank you.

my external device has below characteristics and my clk frequency is 2.048 MHz.What should be my input delay constraints (min and max input delay) ?

Capture.PNG
2.PNG
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avrumw
Guide
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Registered: ‎01-23-2009

First, these appear to be the input timing requirements of the external device. Assuming it is driven by the FPGA, then the outputs of the FPGA are driving the inputs of this device. These outputs should therefore be constrained with set_output_delay commands, not set_input_delay commands.

 

Second, you need to tell us which mode you are using - CLKE=0 or CLKE=1.

 

Next you need to tell us about the clock - is the clock coming from the FPGA (source synchronous) or is the clock on the board fed both to the FPGA and the external device (system synchronous).

 

Rather than pulling the information out of you tiny bit by tiny bit, why don't you take the time to fully describe the problem you have. Tell us what FPGA you are using (family/device/speed grade), what the external device is, what mode it is running in, how they are connected on the board, how you are managing your clock inside the FPGA, what I/O standards you are using, what constraints (if any) you already have, what errors/warnings/timing reports you are getting...

 

Avrum

hrmt
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Registered: ‎06-09-2018

clkE = 1

and external device give clk (RCLKn that is equal to 2.048 MHz ) and data (RDn/RDPn) to FPGA (my fpga is artix7/50t/-2)

i should capture Data (that is RDn/RDPn ) with RCLKn  in FPGA (my fpga clk is RCLKn that is equal to 2.048 MHz).

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avrumw
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Registered: ‎01-23-2009

Your timing diagrams and the timing descriptions distinctly say "Receive Interface Timing". If this interface is a receive interface to your external device they cannot be inputs to your FPGA. There is something that you are misunderstanding.

 

Avrum

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hrmt
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Registered: ‎06-09-2018

block diagram of my external chip is in below image. Is everything right now?

RTIPn and RRINGn signals are inputs to my external chip from another device. RCLKn and RDn are input signals to my FPGA.

Capture.PNG
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avrumw
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Registered: ‎01-23-2009

Sorry - I see now. In addition to the naming, I had looked (only) at t7 and t8 and was interpreting them as PICOseconds, not NANOseconds (so they looked like required setup and hold, rather than provided setup and hold).

 

Because RCLK Pulse Width (t4) is uncertain, there are a couple of ways to calculate the min and max, but with a clock this slow, I will choose the most pessimistic.

 

With CLKE=1, you do have a pretty large hold time issue if you clock the interface with the rising edge of the clock. The easiest way of dealing with this interface is

  - bring the clock in (on a clock capable I/O)

  - use any "legal" clocking scheme (see this post on clocking schemes)

  - ensure that the flip-flops for the inputs are packed into the IOB

  - use the falling edge (not the rising edge) of the clock to capture the data

 

Now for constraints:

 

The timing promised by the external devices is 200ns setup and hold around the falling edge.

 

Since the high time of the clock can be as long as 244ns, this means that it can be as long as 44ns before the data becomes valid after the rising edge of the clock.

 

Similarly, since the data may become invalid 200ns after the falling edge of the clock, and the low phase of the clock can be 244ns long, the data may go away 44ns before the next rising edge of the clock. The reality is that both of these can't occur at the same time, but with an interface this slow, we can afford to be pessimistic.

 

Therefore the timing is

 

set_input_delay -clock [get_ports RCLK] -max 44 [get_ports {RD CV...}]

set_input_delay -clock [get_ports RCLK] -min -44 [get_ports {RD CV...}]

 

This will fail massively if you try and use the rising edge of clock for capture, but will pass easily with the falling edge.

 

Avrum

hrmt
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Registered: ‎06-09-2018

@avrumw

clocking scheme is excellent.

Thank you so much for your great response.

it is very useful.

but some question :

why min input delay is negative?

you said : " ensure that the flip-flops for the inputs are packed into the IOB ". can you explain this (how do i ensure that ff for the inputs are packed into the IOB)?

and when i set input delay constraints my timing requirement not met.

what is the problem?

Capture.PNG
1.PNG
2.PNG
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avrumw
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Registered: ‎01-23-2009

why min input delay is negative?

 

The -min input delay is the earliest time after the edge of the clock that the data can start changing value. In this case, the data can start changing value 44ns before the clock edge, and hence it is negative.

 

can you explain this (how do i ensure that ff for the inputs are packed into the IOB)?

 

You need to be sure that the flip-flop directly and only drives the OBUF, and you need to set the IOB property on the port

 

set_property IOB true [get_ports {<port names>}]

 

and when i set input delay constraints my timing requirement not met.

 

Without seeing the timing path, I can't say, but I suspect you didn't change the RTL to capture the data on the falling edge of the clock (rather than the rising).

 

Avrum

hrmt
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Registered: ‎06-09-2018

@avrumw

 

1- thanks for clear definition of input delay. can you define min and max output delay?

 

2- you said before in here that " ensure that the flip-flops for the inputs are packed into the IOB", but now say : "to be sure that the flip-flop directly and only drives the OBUF" , i don't understand your meant.

 

 3- no on my state machine i capture data on falling edge of clk, my state machine code is here.

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avrumw
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Registered: ‎01-23-2009

1- thanks for clear definition of input delay. can you define min and max output delay?

 

The output delays can be a bit more complicated. Under normal circumstances, the set_output_delay -max is the setup requirement of the device connected to the FPGA, and the set_output_delay -min is the negative of the hold requirement of the device connected to the FPGA (with some allowance for the board propagation times).

 

2- you said before in here that " ensure that the flip-flops for the inputs are packed into the IOB", but now say : "to be sure that the flip-flop directly and only drives the OBUF" , i don't understand your meant.

 

Sorry - those are the rules for an output IOB flip-flop. For an input IOB flip-flop the output of the IBUF must be connected directly (or via an IDELAY) to the D input of a flip-flop. You need the IOB property on the port in both cases.

 

 3- no on my state machine i capture data on falling edge of clk, my state machine code is here.

 

Post the failing detailed timing path.

 

Avrum

hrmt
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Registered: ‎06-09-2018

@avrumw

 in unnormal circumstances what should be happened for output delay, can you explain with an example?

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