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Visitor
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Registered: ‎03-11-2010

timing simulation

I am working on Virtex II pro xc2vp70-71704 device. What is the maximum frequency that can be practically applied to this device? I am using ModelSimXE III 6.4B tool for simulation purpose & Xilinx ISE 8.1i for synthesis purpose. I want to see the the timing simulation of the programs written using vhdl language. Besides creating user constraint file (UCF) using constraints editor, is there any way that the xilinx tool will generate the timing constraints file on its own depending upon the device selected? 

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Historian
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Registered: ‎02-25-2008


mrunal9 wrote:

I am working on Virtex II pro xc2vp70-71704 device. What is the maximum frequency that can be practically applied to this device? I am using ModelSimXE III 6.4B tool for simulation purpose & Xilinx ISE 8.1i for synthesis purpose. I want to see the the timing simulation of the programs written using vhdl language. Besides creating user constraint file (UCF) using constraints editor, is there any way that the xilinx tool will generate the timing constraints file on its own depending upon the device selected? 


You can run the tools without any timing constraints, and it will give you some result, which likely won't be as fast as the part can go.

 

You need to create timing constraints based on your actual requirements, then run the tools against those constraints and then check the timing analyzer to see if you succeed or fail.

----------------------------Yes, I do this for a living.
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