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Adventurer
Adventurer
1,236 Views
Registered: ‎03-15-2016

timing summary report missing input delay resluts

Hi,

The timing summary report don't inlcude the input delay/output delay report, am I right? correct me if I have missing something.

right now, I can see the report with report_timing -from [get_ports ???]

 

Thanks

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Mentor
Mentor
1,227 Views
Registered: ‎02-24-2014

Re: timing summary report missing input delay resluts

If you want to see input and output timing analysis with a standard timing report, you need to add input and output delay constraints.   Without the constraints,  Vivado won't do the timing analysis by default.

Don't forget to close a thread when possible by accepting a post as a solution.
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Guide
Guide
1,185 Views
Registered: ‎01-23-2009

Re: timing summary report missing input delay resluts

Vivado is not ISE...

 

In ISE, you had different TIMESPECs for the internal paths and for the input and output paths. These different TIMESPECs were listed separately in timing reports and the timing summary report had separate sections for reporting paths belonging to these different TIMESPECs.

 

In Vivado, inputs and outputs are not separate constraints. In Vivado, the set_input_delay and set_output_delay commands do not (directly) constrain the paths (as the TIMESPECs in ISE did), but rather provide the tool with the additional information required to "complete the timing path". These provide the tool with the information it needs regarding the system in which the FPGA is going to be used; so

  - what clock is used to launch data to/capture data from the FPGA

  - for an input, how much propagation delay (min and max) that external device (and the board) incur

  - for an output, how much setup and hold that external device (and the board) need

 

With this information the tool times the static timing paths for inputs and outputs using the same constraints and rules it uses for all other paths. Since these paths are not fundamentally different than internal paths, they are not listed separately - they are listed along with all other paths. If they don't show up in the timing summary report, that means that they are not among the worst N paths which are being reported.

 

So, if you explicitly want the timing report from inputs/to outputs, you need to use the Tcl interface to ask for them.

 

Avrum

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Adventurer
Adventurer
1,161 Views
Registered: ‎03-15-2016

Re: timing summary report missing input delay resluts

Hi Avrumw,

    Thanks for detailed description.

    for the source synchronous interface, how could we set the input delay with the setup and hold info from the upstream device.

The UG only tell how to use the trace delay and Tco to set.

 

Thanks

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Adventurer
Adventurer
1,111 Views
Registered: ‎03-15-2016

Re: timing summary report missing input delay resluts

can you help me on this, avrumw.
by the way if i didn't set any input and output condtrains, what will the STA think? THANKS
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