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Registered: ‎11-09-2019

understanding create_clock constraint


I have a xilinx development board that has 50Mhz oscillator frequnecy. I have a design implemented in VHDL. The clk port of my design is connected to oscillator in xdc file. I have also written create_clock constraint of period 20ns(50MHz) in xdc file. 

Is the create clock constarint used only for setup and hold time analysis or will it actually create a clock when the design is implemeted on  FPGA?

The reason why I am asking this is, my design is not meeting timing constraints. So I have to reduce the clk frequency. Now to reduce the frequency, if I create create_clock constraint with less frequency, will that work on FPGA or do I have to write a small chunk of code that would generate lower clock frequecy and pass this new lower frequency clk as input to my design?

Below is the small chunk of code that I referred above.

variable counter : integer := 50000;
if Clk'event and Clk = '1' then
counter := counter - 1;
if counter = 0 then
low_frequency_clk <= not low_frequency_clk;
counter := 50000;
end if;
end if;
end process;

if I simply use create_clock constraint will that work on FPGA or do I have to write above code to really reduce the clock frequency of my design on development borad?

I am new to xilinx timing constraints. Explanation is simple terms will be much helpful.

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4 Replies
Registered: ‎01-22-2015 

The create_clock constraint simply tells Vivado about the port and frequency (period) of a clock entering the FPGA.  That is, the constraint does not actually create the clock - nor can it be used to change the clock frequency.

If you want to change the clock frequency then you must either change the frequency of your external clock oscillator or you must route the clock through one of the Clock Management Tiles (CMTs) found inside the FPGA.


Registered: ‎11-09-2019

Thanks for your answer. I am learning about CMTs. Can you please explain, what would happen if I write the code that I have mentioned in question to generate slower clk and pass that clk as input to my design? Even in that case my design will work on a slower clk right?
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Registered: ‎01-22-2015 

In the VHDL that you have shown, low_frequency_clk, is called a toggle. A toggle is a VHDL signal that looks like a clock but is not a clock and should not be used as a clock.  

Vivado timing analysis works properly only when you have generated and routed clocks in special ways.  The special way used most often is to bring a base clock (yours is 50MHz) into the FPGA on a clock-capable pin and from there route it directly to a CMT (MMCM or PLL).  From the base clock, the MMCM can generate multiple output clocks with frequencies in the range of about 1000MHz down to 4.69MHz - and even lower using a special CLKOUT4_CASCADE feature (see the datasheet for your FPGA).

The easiest way to get a CMT into your design is to use the Vivado Clocking Wizard IP described in Xilinx document PG065.  The Wizard helps you setup the CMT and gives you an instantiation template.  The instantiation template allows you to easily instantiate the CMT into your VHDL in the same way that you would instantiate one VHDL component into another VHDL component.

When you use the Clocking Wizard and a CMT in the way I have described, the Wizard will automatically write the create_clock constraint for your 50MHz base clock.  The Wizard will also automatically write create_generated_clock constraints for the clock outputs of the CMT.

Which FPGA and development board are you using?


Registered: ‎11-09-2019

I am using Xilinx Artix7 (XC7A35T-2CSG324C) FPGA and trenz TRM-TE0711-01 development board. Thanks for the detailed explanation. It cleared many concepts.
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