I studied "ug612.pdf", but I have a lot of questions about that.
Can you introduce me some references(video, pdf, slides...) for better understanding the topics in the "ug612.pdf"?
If i delared an enumrating type signal as below:
Type State is (State1 ,State2 ,State3);
Signal State_Machine : State:=State1;
How can I assign it to "std_logic_vector" signal?
I think what you are trying to do is not about constraint but only about VHDL.
Read a book about VHDL and you will find the answer.