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Adventurer
Adventurer
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Registered: ‎06-17-2016

undrestanding timing constraint

Hi

I studied "ug612.pdf", but I have a lot of questions about that.

Can you introduce me some references(video, pdf, slides...) for better understanding the topics in the "ug612.pdf"?

 

If i delared an enumrating type signal as below:

 

Type State is (State1 ,State2 ,State3);

Signal State_Machine : State:=State1;

 

How can I assign it to "std_logic_vector" signal? 

 

Best Regards

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Moderator
Moderator
532 Views
Registered: ‎11-09-2015

Re: undrestanding timing constraint

Hi @dariush84,

 

I think what you are trying to do is not about constraint but only about VHDL.

 

Read a book about VHDL and you will find the answer.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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