09-17-2019 04:28 AM
I have basic problem with understanding the behaviour of an FPGA. In my case its a artix-7 XC7A35T. I want to realize 10 parallel SPI interfaces (small and straight forward VHDL coded) to read some ADCs. The SPI modul clock frequency is 200 Mhz generated from an external 100 MHz source through the clock wizard. The SPI communication clock is 25 Mhz. All interfaces are started at the same time.
The problem now is, that the SPI communication get faulty and unstable the moment I cross an specific amount of SPI modules that are implemented. Are there some regulations to the load of a certein clock or the chip itself?
09-17-2019 04:50 AM
Is this a commercial board or custom? If custom, is it decoupled in accordance with the Xilinx layout guidelines? Have you looked to see if you are getting voltage droop or noise if you add more SPI busses? Do you have timing constraints for your design? When you say "add more SPI modules" do you mean add more to the design or just turn on one that is already there?
09-17-2019 05:17 AM
It is a commercial board and I assume they done the decoupling properly.
I will check for voltage drops or noise, but I would assume, if this would be a problem all of the FPGA operations would be unexpected. But its just the SPI modules.
I have a clock port for the external clock source and all internal clocks coming from the clocking wizard block. I dont use the external clock directly. But I do not have a timing constraints file or such thing. Should I realise this getting near such frequencies?
Add more SPI modules mean coding them into my VHDL main file. It does not matter if they are working or not.
09-18-2019 04:16 AM
Timing constraints always matter. You may have gotten away with it in the past simply because the design was uncongested and Vivado had no trouble routing to very tight timing. Adding more modules will obviously add congestion, and will then cause more interesting timing problems.
09-18-2019 04:37 AM
Due to your comment, I read a lot about timing constraints. Now I understand their importance and already improved my design. As you mentioned correctly, Vivado covered up a lot in the past and I will revise this code in the near future. Thank you for pointing me in the right direction.
09-18-2019 09:35 AM
1) Are you generating a 25MHz SCK with a PLL or just divide the system clock by 8 with a counter in your VHDL code and SCK is like any other output signal?
2) If the latter, are you using 10 separate SCK signals for 10 ADCs or just one common one?
3) If the latter, you might want to set the IO pin parameters for max current, speed, slew rate.
By the way, if all ADCs are the same type, you might need just one wire to broadcast one common config to all of them. ;-) If the load will not be a problem.
09-18-2019 09:38 AM