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justinz
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Registered: ‎11-14-2017

vivado check timing Register/Latch pins with no clock driven by root clock pin: dbg_hub/sl_iport0_o[1]

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FPGA: ultrascale 440

vivado version: vivado 2016.2

 

problem description: the post synthesis check timing shows there are 137 endpoints no clock . These endpoints are all in a ddr3 ip. I have add the ddr3 clock constraint in xdc. is there any solution of this problem? 

 

Register/Latch pins with no clock driven by root clock pin: dbg_hub/sl_iport0_o[1] (137)
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[10]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[11]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[12]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[13]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[14]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[15]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[16]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[2]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[3]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[4]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[5]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[6]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[7]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[8]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[9]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[11]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[12]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[13]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[15]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[2]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[4]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[5]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[7]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[8]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[9]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[10]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[11]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[12]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[13]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[14]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[15]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[2]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[3]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[4]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[5]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[6]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[7]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[8]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[9]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_drdy_r_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_dwe_r_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[10]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[11]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[12]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[13]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[14]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[15]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[2]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[3]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[4]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[6]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[7]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[8]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[9]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_drdy_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[10]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[11]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[12]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[13]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[14]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[2]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[3]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[4]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[5]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[6]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[7]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[8]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[9]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[9]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_cmd_en_r_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_sclk_r1_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_sclk_r2_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[1]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/C
u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[1]/C

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hemangd
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Registered: ‎03-16-2017

Hi @justinz,

 

You need to check in your RTL that why this registers (mentioned in the Timing-17 warnings) does not have clock and make necessary changes. 

 

Or you can also provide us the archived project to find out the root cause.

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

View solution in original post

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anjaneyulu.challa9
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Registered: ‎04-11-2017

Can you check whether the constraint provided in the xdc is applied by running it in the tcl console (with Synthesized or implemented design) ?

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hemangd
Moderator
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Registered: ‎03-16-2017

Hi @justinz,

 

1. Are you using timing exceptions in your design? If yes, please provide the constraints file. 

2. Run "report_methodology" after implementation stage completes and provide the report to see what warnings you are facing with high severity.  

 

Usually this warning occur due to the segmentations in your clock tree. And multiple segmentation occur due to your wrongly applied timing exceptions. 

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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justinz
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Registered: ‎11-14-2017

I am not using any time exceptions in my design except "set_clock_groups -asynchronous " constriant of primary clocks.

It will cost 2 days to complete implement step and probably  failed for timing issues. 

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hemangd
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Registered: ‎03-16-2017

Hi @justinz,

 

Okay, than you can do the same after synthesis also. 

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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justinz
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Registered: ‎11-14-2017

the project xdc file has been applied, but I am not sure whether the ddr3 ip xdc have been applied . which tcl  command can check this ? below is the check timing summary report of post synthesis

 

check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
There are 137 register/latch pins with no clock driven by root clock pin: dbg_hub/sl_iport0_o[1] (HIGH)


2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 156 pins that are not constrained for maximum delay. (HIGH)

There are 7767 pins that are not constrained for maximum delay due to constant clock. (MEDIUM)


5. checking no_input_delay
--------------------------
There are 84 input ports with no input delay specified. (HIGH)

There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
There are 102 ports with no output delay specified. (HIGH)

There are 0 ports with no output delay but user has a false path constraint

There are 4 ports with no output delay but with a timing clock defined on it or propagating through it (LOW)


7. checking multiple_clock
--------------------------
There are 2 register/latch pins with multiple clocks. (HIGH)


8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input

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viviany
Xilinx Employee
Xilinx Employee
4,191 Views
Registered: ‎05-14-2008

"There are 137 register/latch pins with no clock driven by root clock pin: dbg_hub/sl_iport0_o[1] (HIGH)"

 

dbg_hub/sl_iport0_o[1]

This looks like a net in dbg_hub core.

This core is automatically inserted when you add debug cores in your design like ILA.

Can you pick up one of these 137 pins and open it's schematic in the synthesized design. And trace back from its C pin to see what is driving the C pin?

 

-vivian

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justinz
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Hi,hemangd

    

   The related warnings in methodlogy report of post synthesis are as follows: 

TIMING-17#21 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[0]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#22 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[10]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#23 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[11]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#24 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[12]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#25 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[13]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#26 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[14]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#27 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[15]/C is not reached by a timing clock
Related violations: <none>

 

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justinz
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Registered: ‎11-14-2017

Hi vivian

            I found 1 of the related pins in the post synthesis schematic as follow. Its C pin is empty connected with nothing .

           I thought this net should be connected with drive clock automatically when it's generated by IP generator.

           

cpin.png
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justinz
Visitor
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Registered: ‎11-14-2017

Hi ,hemangd

 

     part of  methodlogy report of post synthesis is as follow:

TIMING-17#21 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[0]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#22 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[10]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#23 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[11]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#24 Warning
Non-clocked sequential cell
The clock pin u_tp9001_wop/u_tp9001_cor/u_mdmc_umctl2_wrap/u_ddr3_0/inst/u_ddr3_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[12]/C is not reached by a timing clock
Related violations: <none>

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hemangd
Moderator
Moderator
4,463 Views
Registered: ‎03-16-2017

Hi @justinz,

 

You need to check in your RTL that why this registers (mentioned in the Timing-17 warnings) does not have clock and make necessary changes. 

 

Or you can also provide us the archived project to find out the root cause.

 

Regards,

hemangd

Regards,
hemangd

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justinz
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Registered: ‎11-14-2017

Hi ,hemangd

         I checked the driving clock in RTL ,the driving clock is connected to 0 in ddr3 ip. 

         thanks for your help.

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justinz
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Registered: ‎11-14-2017
Hi, vivian
thanks for your reply ,it's solved for the clock is connected to 0 in rtl.
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