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Registered: ‎07-09-2009

vivado ? some signals stable for one clock, some for two

Loking at a design  in a kintex 7,


interfacing to a processor,

   processor feeds out a 200 MHz clock with the data, 

      have some signals that change on each clock, so have constrained them normaly,


but have some signals that are present for two clocks,

    so I can give them more time to settle 

        but still needs to be aligned to the clock,


how can I say this pin has two clock cycles to settle , do I need to look at mutli cycle paths ?


for refernace

all signals,


clk is 200 MHz,

   data is valid 3ns after rising edge of clk and held for 1.5 ns


and as per the questoin , some signals are stable in for one clock , some for two.


and this is what I have for clock and the single clock wide signals


create_clock -period 5.000 -name clk_a -waveform {0.000 2.500} [get_ports CLK_pin]

set_input_delay -clock [get_clocks clk_a] -min 1.500 [get_ports {ADD[0]}]
set_input_delay -clock [get_clocks clk_a] -max 3.000 [get_ports {ADD[0]}]



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