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Voyager
Voyager
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Registered: ‎10-12-2016

what are the different ways to provide clock ref to MMCM and PLL for 7 series FPGAs?

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HI Friends, 

Most of times i will use only IO Clk pads for MMCM/PLL ref clocks, But i read in UG472 as "MMCM/PLL has multiple resources for ref clock". 

what are the different ways to provide clock ref to MMCM and PLL for 7 series FPGAs?

 

Any help or suggestions are highly appreciated. 

Thank You 

S Sampath

 

 

-Sampath
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Explorer
Explorer
648 Views
Registered: ‎07-18-2018

In the UG you can look up the details of the primtive inputs/outputs. On page 80 for example: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

CLKIN1 – Primary Reference Clock Input:

CLKIN1 can be driven by SRCC or MRCC I/O directly within the same clock region, SRCC or MRCC I/O through the CMT backbone in a vertically adjacent clock region, BUFG, BUFR, BUFH, interconnect (not recommended), or directly by a high-speed serial transceiver. When the clock input is coming from another CMT block for cascading CMT functions, only CLKOUT[0:3] can be used.

CLKIN2 – Secondary Clock Input:

CLKIN2 is a secondary clock input that is used to dynamically switch the MMCM/PLL reference clock. CLKIN2 can be driven by SRCC or MRCC I/O directly within the same clock region, SRCC or MRCC I/O through the CMT backbone in a vertically adjacent clock region, BUFG, BUFR, BUFH, interconnect (not recommended), or directly by a high-speed serial transceiver

 

You can see all the ways that you can drive the pin other then an IO port.

View solution in original post

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Explorer
Explorer
649 Views
Registered: ‎07-18-2018

In the UG you can look up the details of the primtive inputs/outputs. On page 80 for example: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

CLKIN1 – Primary Reference Clock Input:

CLKIN1 can be driven by SRCC or MRCC I/O directly within the same clock region, SRCC or MRCC I/O through the CMT backbone in a vertically adjacent clock region, BUFG, BUFR, BUFH, interconnect (not recommended), or directly by a high-speed serial transceiver. When the clock input is coming from another CMT block for cascading CMT functions, only CLKOUT[0:3] can be used.

CLKIN2 – Secondary Clock Input:

CLKIN2 is a secondary clock input that is used to dynamically switch the MMCM/PLL reference clock. CLKIN2 can be driven by SRCC or MRCC I/O directly within the same clock region, SRCC or MRCC I/O through the CMT backbone in a vertically adjacent clock region, BUFG, BUFR, BUFH, interconnect (not recommended), or directly by a high-speed serial transceiver

 

You can see all the ways that you can drive the pin other then an IO port.

View solution in original post