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yuz835
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Registered: ‎04-12-2018

what are these delays? lut50425_14952

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Maximum Data Path at Slow Process Corner: slave_i/mem_bridge_i/waddr_2 to slave_i/reg_if_inst0/reg_506_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X74Y77.AQ      Tcko                  0.408   slave_i/ram_i/waddr_i<3>
                                                       slave_i/mem_bridge_i/waddr_2
    SLICE_X91Y65.B5      net (fanout=87)       1.651  slave_i/ram_i/waddr_i<2>
    SLICE_X91Y65.B       Tilo                  0.259   slave_i/mem_bridge_i/gen_f[1].f_inst/reg_6d<3>
                                                       lut50425_14952
    SLICE_X74Y83.A2      net (fanout=35)       9.821   lut50425_14952
    SLICE_X74Y83.A       Tilo                  0.205   lut34810_9682
                                                       lut113263_32508
    SLICE_X65Y87.A6      net (fanout=5)        1.551   lut113263_32508
    SLICE_X65Y87.A       Tilo                  0.259   lut113319_32539
                                                       lut113319_32539
    SLICE_X73Y85.CE      net (fanout=2)        1.205   lut113319_32539
    SLICE_X73Y85.CLK     Tceck                 0.295   slave_i/reg_if_inst0/reg_506<7>
                                                       slave_i/reg_if_inst0/506_7
    -------------------------------------------------  ---------------------------
    Total                                     15.654ns (1.426ns logic, 14.228ns route)
                                                       (9.1% logic, 90.9% route)

 

I have a long path caused not able to close timing at 10ns,

there are some strange LUT delays in colored red

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jmcclusk
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Registered: ‎02-24-2014

Ouch... this is a much tougher problem to solve on Spartan6 with ISE.    I'm guessing that you may have trouble pipelining this data path, but if it all possible, that's the easiest way to fix the problem.   If you can't pipeline it, then it may be possible to use PlanAhead to do a little gentle floorplanning on the start & stop elements of this timing path.

 

But first,  I'd open the design in FPGA editor and then use the cross-probing feature to look at the routing path.   That may yield something interesting. 

Don't forget to close a thread when possible by accepting a post as a solution.

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jmcclusk
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Registered: ‎02-24-2014

This is the routing net that is killing your timing closure:

 

SLICE_X74Y83.A2      net (fanout=35)       9.821   lut50425_14952

 

you need to investigate why a net with a fanout of 35 has such a high delay.  What tool are you using (ISE or Vivado)?

 

What device and speed grade are you targeting?  

 

I'm guessing from the high delay number alone, that this is a Spartan device with ISE..    Vivado rarely gives numbers like this.

Don't forget to close a thread when possible by accepting a post as a solution.
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yuz835
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Registered: ‎04-12-2018
you are rite,
Spartan6 device with ISE, any suggestion on investigation?
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jmcclusk
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1,518 Views
Registered: ‎02-24-2014

Ouch... this is a much tougher problem to solve on Spartan6 with ISE.    I'm guessing that you may have trouble pipelining this data path, but if it all possible, that's the easiest way to fix the problem.   If you can't pipeline it, then it may be possible to use PlanAhead to do a little gentle floorplanning on the start & stop elements of this timing path.

 

But first,  I'd open the design in FPGA editor and then use the cross-probing feature to look at the routing path.   That may yield something interesting. 

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

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yuz835
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Registered: ‎04-12-2018

thanks, I guess I can pipeline it

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