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Voyager
Voyager
352 Views
Registered: ‎10-12-2016

what constraints we have to use for synchronus clock with different frequencies ?

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HI Friends,

I have two clocks which are generated from the same source clk24 and clk20.

i have path like clk24 to clk20. am getting hold issue on this path, what constraints i have to use ?

clk24_to_clk20.png

 

For any help or suggestions are highly appreciated.

Thank You

S Sampath

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1 Solution

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Adventurer
Adventurer
293 Views
Registered: ‎05-09-2018

Re: what constraints we have to use for synchronus clock with different frequencies ?

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I am not sure what your design looks like so it is hard to tell.

In general with FPGAs one should constrain the period of the source clock rather than the clock module outputs. The tools will figure out the output rates for the rest of it.

Normally if one clock is say 2x the other this is all you need.

In your instance you probably need to treat this as an async clock handoff (or timing closure may be a problem) and use a valid clock domain  crossing method to hand data between the sides. 

Once the Method is understood the additional constraints can be as simple as a false path at the CDC flops.

 

2 Replies
Explorer
Explorer
300 Views
Registered: ‎07-18-2018

Re: what constraints we have to use for synchronus clock with different frequencies ?

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Hi ssampath,

   How are you handling the crossing between the paths? The SRC clock is faster then the DST. So it will be producing data slightly more often then the DST side. So over 100 Cycles, the other side could only potentially sample about 83 of them.

Depending how you handle the clock crossing, the correct way to constrain it will be different.

 

 

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Adventurer
Adventurer
294 Views
Registered: ‎05-09-2018

Re: what constraints we have to use for synchronus clock with different frequencies ?

Jump to solution

I am not sure what your design looks like so it is hard to tell.

In general with FPGAs one should constrain the period of the source clock rather than the clock module outputs. The tools will figure out the output rates for the rest of it.

Normally if one clock is say 2x the other this is all you need.

In your instance you probably need to treat this as an async clock handoff (or timing closure may be a problem) and use a valid clock domain  crossing method to hand data between the sides. 

Once the Method is understood the additional constraints can be as simple as a false path at the CDC flops.