12-23-2008 07:05 PM
1. what is clock regions in the ISE9.1i FPGA editor?
2. what function it is?
3. commpare with ISE7.1i, why add this new function?
12-24-2008 05:51 AM
1) Clock Regions in FPGA Editor show/highlight the clock regions in the FPGA part.
2) Clock Regions are the fundamental part of FPGA that allow for zero skew clock distribution across the part. In the Virtex series of parts, the clock regions describe the availability of the global clock throughout the chip. Each clock region has a maximum amount of number of global clocks that can be routed into the area. Most of the current Virtex parts have a maximum of 8 global clocks per region.
Now you're probably asking yourself why you have a smaller number of global clocks per region than the maximum per part. That's because all of the clocks are not necessarily needed throughout a whole design, thereby allowing an FPGA designer to partition the clock usage into the regions known as the Clock Regions (wait didn't we just discuss those? :)).
3) No idea about this once since I don't have ISE 7.1 installed, but I'd bet that it was in there too, you may have just missed it.