07-14-2020 09:20 PM
I have generated master clock by using below-mentioned options in the constraint file
and generated clock by the below-described way in the constraint file
but while reporting timing between these 2 paths, delays from the master clock to generated clock is not been considered
Please let me know what options can I use to include delays from the master to the generated clock.
07-14-2020 09:46 PM - edited 07-14-2020 09:49 PM
First, neither of these two clocks should have the -add option. Its probably harmless on the first one, but is probably not on the create_generated_clock; depending on what the propagation path is, you may end up with both the source and the generated clock on any path downstream from the generated clock.
Second, you should (pretty much) never have a create_clock inside the FPGA. Primary clocks (create_clock) should only be attached to
These represent the only ways of getting clocks into your FPGA - all other clocks should be derived from these, either automatically or using create_generated_clock commands.
As for the timing on paths that cross these clock domains (which one should be very careful with - you probably shouldn't be doing normal synchronous clock crossing between these two domains), I can't tell what the problem is without seeing the timing report. I would fix the above issues first, and then, if the problem is still there post a timing report.
But one possible comment; Vivado reports timing on timing paths; from a startpoint (a clocked element or input port) to an endpoint (a clocked element or an output port). The design elements to which your clocks are attached are neither, and hence you cannot report timing on them directly. The timing of the clocks, however, will show up in the timing paths of any path that uses these clocks to clock the startpoint and/or endpoint (as the source clock path and destination clock path respectively).
07-14-2020 10:14 PM - edited 07-14-2020 11:58 PM
As I could find the -add option description in vivado is as follows -
In my opinion, I don't think that -add option will create any issue
Also when I tried to create_generated clock without -add option vivado reported an error
07-15-2020 07:30 AM
The description for the -add option you posted is not the same as either my understanding or the description in newer versions of Vivado - here is what it says in 2019.1
-add - (Optional) Define multiple clocks on the same source for
simultaneous analysis with different clock waveforms. Use -name to specify
the new clock to add. If you do not specify this option, the create_clock
command will automatically assign a name and will overwrite any existing
clock of the same name.
This means that the new clock will be added to the pin/port/net which is the <object> of the command; thus if this pin/port/net already has a clock on it, then there will now be two clocks on it. In most cases this is not what you want - the generated clock should be the only clock on this pin/port/net.
Also in the command it states
Note: -add and -name options must be specified with -master_clock.
which I have never understood (and seems like a bug), but it generally isn't a big deal. The use of the -master_clock option is rarely needed. You only need the -master_clock option if the pin/port/net that is specified as the -source has more than one clock on it; in this case, you need to tell it which of the multiple clocks on the -source object to use for the generated clock. It is pretty rare to have more than one clock on a given object (unless you accidentally overuse the -add option!), so you rarely need the -master_clock option. If you don't use the -master_clock option, you don't need the -add option, and, as I stated above, you don't want to use the -add option.