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microchip_zhang
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Registered: ‎08-15-2017

when using axi vdma ,the timing fail ?

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please refer to the attachment ,how to impove the timing of the vdma below in the figure, can impove the timeing via inserting reg in the combinatorial logic  like axi interconnect IP ? or the logic out of the vdma ip cause the failure

 

 

 

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florentw
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Registered: ‎11-09-2015

HI @microchip_zhang 

In the latest version of the AXI VDMA there is no scatter gather so you will not face this timing issue. So I suggest you move to a newer vivado version.

There is no more support for the version you are using


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

Hi @microchip_zhang 

There is not much detail to help. How the VDMA is connected? What clock is used? Are you using the same clock for all the interfaces?

Did you see AR#71984?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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microchip_zhang
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Registered: ‎08-15-2017

I think the *.xdc file of the vdma is functional, according to the figure shown below, and the the vivado version I am using is 2014.4

 

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microchip_zhang
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Registered: ‎08-15-2017

now I have edit the self-defined IP , but now the timing fail is in axi interconnect , I have add the register slice using the IP wizard of the axi interconnect,but still timing can not be satisfied ,the figure shown  below is the timing report of synthesis

 

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microchip_zhang
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Registered: ‎08-15-2017

the timing report of implementation has warning

 

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microchip_zhang
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Registered: ‎08-15-2017

axi VDMA is connected to axi interconnect1 directly,  vdma  and axi interconnect1 all use FCLK0 which outputs by processing system of zynq.

what is the  reason of  timing fail ? besause the self-defined IP  or there are other reasons ?

all the IP including self-defined IP  , axi interconnect, and  axi vdma  work using the FCLK0 which outputs by processing system of zynq, the fequency is 200mhz,

how to impove the timing

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florentw
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250 Views
Registered: ‎11-09-2015

HI @microchip_zhang 

In the latest version of the AXI VDMA there is no scatter gather so you will not face this timing issue. So I suggest you move to a newer vivado version.

There is no more support for the version you are using


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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