Thank you very much.But I do not understand the words with red line in the figure below, why transmits the signal from one FF to the next FF in 0.75 period , a timing violation will not be created, but in 0.25 period , a timing violation then will be created ,just for 0.25 period is less than 0.75 period? in general in one whole period, the timing violation will not be created after being handled to satisfy the timing constrains by the vivado
Let's take the example of running at 400MHz (which is generally possible for small amounts of logic in the FPGA).
The requirement on a path at 0.75 clocks is 1.88ns. It is almost certainly possible for the placer and router to make a 1.88ns flip-flop to flip-flop path work.
But a path at 0.25 clocks is 0.625ns. This needs to account for the clock skew between the flops (including the clock skew due to the fact that they are two different clocks, CLK and CLK90), the clock to output delay of the first flip-flop, the routing between the two flip-flops (which is dependent on the placement) and the setup requirement of the second flip-flop. This may not be doable in 0.625ns.
So, yes, there are cases where a 0.75x clock period path is easy to meet where a 0.25x clock period is much harder or impossible.