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Voyager
Voyager
324 Views
Registered: ‎10-12-2016

why clock is connected to data pin of flop ?

Hi Friends, 

I am not understanding schematic view vs my code while analysing the hold path. clock net connected to data pin of the flop. Can any one help on this?

h1.PNGcode1.PNG

NOTE: Any help or suggestions are highly appreciated. 

-Sampath
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5 Replies
Moderator
Moderator
302 Views
Registered: ‎03-16-2017

Re: why clock is connected to data pin of flop ?

Hi @ssampath ,

Can you post your full code to investigate?

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Voyager
Voyager
289 Views
Registered: ‎10-12-2016

Re: why clock is connected to data pin of flop ?

how can i send securely ?
-Sampath
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Xilinx Employee
Xilinx Employee
258 Views
Registered: ‎05-14-2008

Re: why clock is connected to data pin of flop ?

We need to know how i_adc_ext_trig is coded.

And how are CLR and CE connected for the FDCE in the netlist?

-vivian

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Voyager
Voyager
251 Views
Registered: ‎10-12-2016

Re: why clock is connected to data pin of flop ?

clk_to_data_may27.PNG

-Sampath
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Xilinx Employee
Xilinx Employee
233 Views
Registered: ‎05-14-2008

Re: why clock is connected to data pin of flop ?

Which net in the image above is "adc_reset_n"?

Can you post the code that generates "i_adc_ext_trig"?

We have an EZMOVE system that you can use to send files securely, can you send me your source files with EZMOVE? Make sure that those files can be used to reproduce the issue at my end.

-vivian

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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