05-25-2019 10:09 PM
I am not understanding schematic view vs my code while analysing the hold path. clock net connected to data pin of the flop. Can any one help on this?
NOTE: Any help or suggestions are highly appreciated.
05-26-2019 12:13 AM
05-27-2019 02:31 AM
We need to know how i_adc_ext_trig is coded.
And how are CLR and CE connected for the FDCE in the netlist?
05-27-2019 11:04 PM
Which net in the image above is "adc_reset_n"?
Can you post the code that generates "i_adc_ext_trig"?
We have an EZMOVE system that you can use to send files securely, can you send me your source files with EZMOVE? Make sure that those files can be used to reproduce the issue at my end.