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Voyager
Voyager
687 Views
Registered: ‎10-12-2016

why tool doing hold analysis between MMCM and FF ?

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HI Friends,

Am getting hold violations on a MMCM to FF. I am understanding clearly why tool doing on this path.

Can you please help or suggest to understand this ?

NOTE:  Any help or suggestions are highly appreciated.

Schematic2019-07-03 07-30-23.pngtiming_info_part1 2019-07-03 07-31-42.pngtiming_info_part22019-07-03 07-32-23.png

-Sampath
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Moderator
Moderator
500 Views
Registered: ‎01-05-2017

Hi @ssampath 

Is it an UltraScale device that you are targeting?

One way to generate the clocks you want is to use an MMCM and a bufgce_div and set the divide factor accordingly.

For example:

The 100MHz feeds into your MMCM. Configure your MMCM to output a single 50MHz clock. In your RTL instansiate 3 bufgce_div's in parallel. Connect the 50MHz clock output of the MMCM to the input of each of the 3 bufgce_div's. Set the divide factor of the first bufgce_div to 1, the second bufgce_div to 2 and the 3rd bufgce_div to 4. This will give you your 50MHz, 25MHz and 12.5MHz clocks. This method will also help the tool manage skew between the clocks.

See UG572 for details on the bufgce_div.

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Moderator
Moderator
682 Views
Registered: ‎11-04-2010

Hi, @ssampath ,

Genenrally MMCM's output clock is used to drive the C(clock) pin of FF.

If you avoid using MMCM's output clock to drive the D pin of the FF, there will be no analysis from MMCM to FF.

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Voyager
Voyager
632 Views
Registered: ‎10-12-2016

Hi@hongh ,

Thank You,

But we used this in clock divider logic. we have many clock divider logic modules are there. Please let me know best way to code it. 

 

-Sampath
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Moderator
Moderator
620 Views
Registered: ‎11-04-2010

Hi, @ssampath ,

I don't think the hold time of the reported path should be analyzed.

You can set_max_delay -datapath_only on this path to avoid hold time violation.

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Moderator
Moderator
610 Views
Registered: ‎03-16-2017

Hi @ssampath , 

A good way to do a clock divider is to use a BUFGCE primitive (see UG472 p42 and UG768 p77). Controlling the CE pin will help you to divide the clock.

Regards,
hemangd

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Guide
Guide
592 Views
Registered: ‎01-23-2009

You can set_max_delay -datapath_only on this path to avoid hold time violation.

This is very dangerous, and shouldn't be done - this is merely turning off the correct and important warning.

Your design is not safe. You should not drive the data pin (i.e. a non-clock pin) of a flip-flop with a clock. The FPGA has dedicated clock resources for routing clocks, with roots at clock buffers and leaves at the clock pins of flip-flops. While other connections are structurally legal (leaves to non-clock pins, roots from not clock sources), there are very few cases where these should be used (for example using a global clock network to buffer a high fanout data signal). What you are doing is definitiely not one of those cases.

If you need a divided clock, this is not the way to do it. There are a couple of ways of doing them:

  • Use the main clock, and generate an "enable" signal for the flip-flops that you want to have run at a slower rate. For each of these use code like the code below
    • the "divder_enable" is a normal synchronous signal that is enabled one out of N clock periods - the most common way of implementing it is enabling it when a reloadable down counter reaches 0 (from N-1)
always @(posedge clk)
begin
  if (rst) begin
    // reset stuff
  end
  else if (divider_enable)
  begin
    // Stuff running at the "divided" rate
  end
end
  • Use a similar structure for the divider_enable, but use a BUFGE or a BUFHCE for generating a decimated clock on a dedicated clock net
  • In some cases (but I don't recommend it) you can geneate a divided clock in the fabric (by a sequential divider) and then route the output of that to another BUFG
    • This is not recommended due to the excessive skew between the base clock and the divided clock

However, even the last one (which is not recommended) does not require the output of the MMCM to be routed to the D input of a flop - the divider itself is a normal sequential divider.

Routing from the MMCM to the D input of a flip-flop creates timing problems. The tools are warning you about that - they are right! Do not simply disable the warning - fix the problem.

Avrum

Voyager
Voyager
567 Views
Registered: ‎10-12-2016

Hi @avrumw ,

 

Thank you, still am not clear how it will generate required clocks. 

suppose i have 100MHz clock source. i want to generate 50(100/2),25(100/4),12.5(100/8) clocks.  Can you please exapliain how to generate these ? and i have path relation between 100Mhz and 50Mhz, and between other clocks also. 

 

-sam

-Sampath
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Moderator
Moderator
501 Views
Registered: ‎01-05-2017

Hi @ssampath 

Is it an UltraScale device that you are targeting?

One way to generate the clocks you want is to use an MMCM and a bufgce_div and set the divide factor accordingly.

For example:

The 100MHz feeds into your MMCM. Configure your MMCM to output a single 50MHz clock. In your RTL instansiate 3 bufgce_div's in parallel. Connect the 50MHz clock output of the MMCM to the input of each of the 3 bufgce_div's. Set the divide factor of the first bufgce_div to 1, the second bufgce_div to 2 and the 3rd bufgce_div to 4. This will give you your 50MHz, 25MHz and 12.5MHz clocks. This method will also help the tool manage skew between the clocks.

See UG572 for details on the bufgce_div.

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