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Registered: ‎02-12-2018

wrong timing requirement 0.000 while 1.500 expected

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Hello,

 

With an implemented design open, I have my source synchronous input DDR interface constrained for 142MHz:

DDR_RX_142MHz.png

 

If I set 333MHz, instead, I get the following:

DDR_RX_333MHz.png

 

In the column "Requirement" it says 0.000, I would have expected 1.500.

 

constraints where defined as

create_clock -name HDMI_RX_CLK_P -period 3.0 [get_ports HDMI_RX_CLK_P]

set_input_delay -clock HDMI_RX_CLK_P -max [expr 1.6] [get_ports HDMI_RX_P*];
set_input_delay -clock HDMI_RX_CLK_P -min [expr 1.4] [get_ports HDMI_RX_P*];
set_input_delay -clock HDMI_RX_CLK_P -max [expr 1.6] [get_ports HDMI_RX_P*] -clock_fall -add_delay;
set_input_delay -clock HDMI_RX_CLK_P -min [expr 1.4] [get_ports HDMI_RX_P*] -clock_fall -add_delay;

why is it constrained with 0.000 ns?

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thakurr
Moderator
Moderator
874 Views
Registered: ‎09-15-2016

Hi @theultimatesource

 

To my understanding for DDR interface with 333 MHz clock, the set up requirement is expected to be 1.5 ns while hold requirement is 0 ns. The hold requirement is calculated one clock edge before to the set up. For hold, data is launched and captured on same clock edge for ideal scenario.

Regards
Rohit
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thakurr
Moderator
Moderator
875 Views
Registered: ‎09-15-2016

Hi @theultimatesource

 

To my understanding for DDR interface with 333 MHz clock, the set up requirement is expected to be 1.5 ns while hold requirement is 0 ns. The hold requirement is calculated one clock edge before to the set up. For hold, data is launched and captured on same clock edge for ideal scenario.

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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View solution in original post