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Explorer
Explorer
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Registered: ‎08-23-2011

xilinx 14.1 timing report worst case slack and best case mis-match ...

hi,

 

i have a design which ive implemented using ISE 14.1 on a virtex6 device. when i look at the final design summary, i have 2 constraints that are not met.

 

clk1, constrained to 150MHz (6.66ns) - ISE says setup slack = -7.858ns, best case achievable = 14.46ns (i.e. 6.66ns + 7.8ns)

clk2, constrained to 150MHz (6.66ns) - ISE says setup slack = -4.3ns, bes case achievable = 16.31ns

 

there are no hold time violations (i.e. +ve slack in the timing report)

 

for clk1, as can be seen, the setup slack and the period add up to give the best achievable freq.

but for clk2, the setup slack and clk constraint donot add to give 16.31ns ... i was wondering how the tool is managing to get to 16ns?

 

and which value should i give more importance to? the setup slack or the best case achievable?

 

thanks for inputs,

 

z.

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Scholar
Scholar
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Registered: ‎02-27-2008

z,

 

When you do not meet timing, I would not take any numbers seriously:  until you have positive slack, the numbers are generally worthless.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
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Registered: ‎08-23-2011

hi austin,

 

its interesting that you'd say that because i would think the reason Xilinx has put the worst case slack and best case achievable fields in the report is to indicate the best the current design (with the current constraints) can do in terms of nets and frequencies.

 

also, when i look at the verbose timing report for the failing paths, Xilinx still shows a worst case slack of -4.8ns on some paths and it shows all the routing and logic delay which brought down the design to a -ve slack of 4.8ns

 

so would the above not mean that the worst case slack, (because the tool shows how it is arriving at the worst case slack), indicates that the worst case slack has "some" more credence (if not 100%) as compared to the best case achievable field?

 

do let me know what you think ...

 

Thanks and regards,

Z.

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Scholar
Scholar
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Registered: ‎02-27-2008

z,


If it isn't positive (meets timing) then the information is worthless.


My opinion of course, but I am basing that on my 17 years of working with FPGA designs here at Xilinx, and my many years before than using them in industry.

 

More to the point, if the design does not meet timing, what useful information is even possible?

 

The only way I know to find the actual perofrmance of a design is start at a period constraint that is easily met, and the decrement it until it is not met.  Then, take the previous constraint that did meet, and decrement it in an even smaller step until it doesn't succeed.


Then continue decrementing (as there are solutions for even faster constraints after the first failing one).

 

Generally, the idea is to do no more work that is needed, so finding the optimal solution is not the task.  The task is to find one acceptable solution.

 

If a solution is not acceptable, its data is worthless in my opinion,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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