UG903 p.139 "set_bus_skew Example One" presents and explains a similar scenario, but I am not sure to have understood 100%.
Note: it is a slight different case, because the number of syncstages_ff_reg* is considered, and not the usual dest_hsdata_ff_reg*, but should use the same reasoning. For reference, dest_clk_period = 2.5ns, so the max bus_skew is set to 4x2.5ns, as well as the set_max_delay -datapath_only.
According to the explanation, the set_bus_skew analyses the skew between capture times (destination FF) of all bus paths.
To calculate this "capture time", I would think that Vivado accounts for:
net_delay (datapath_only) delta between bus paths
clock skew between destination FFs (not the usual source -> destination clock skew)
Therefore, what I think they are trying to constrain is the clock_skew delta, because the max_net_delay delta is already 10ns (set_max_delay ... 4*2.5 -datapath_only).
A violation scenario where dest_hsdata_ff_reg is close to sample old data: