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Registered: ‎08-11-2017

xpm_cdc_handshake set_bus_skew constraint

I am trying to understand the xpm_cdc_handshake.tcl constraints in: Vivado/<version>/data/ip/xpm/xpm_cdc/tcl directory.

Apparently, there is a set_max_delay -datapath_only followed by a set_bus_skew that is generally applied:

 

set_max_delay -from [get_cells src_hsdata_ff_reg*] -to [get_cells dest_hsdata_ff_reg*] [expr {$dest_clk_period * $xpm_cdc_hs_num_s2d_dsync_ff}] -datapath_only
set_bus_skew  -from [get_cells src_hsdata_ff_reg*] -to [get_cells dest_hsdata_ff_reg*] [expr {$dest_clk_period * $xpm_cdc_hs_num_s2d_dsync_ff}]

 

UG903 p.139 "set_bus_skew Example One" presents and explains a similar scenario, but I am not sure to have understood 100%. 

 

Screenshot from 2018-01-13 03-04-18.png

 

Note: it is a slight different case, because the number of syncstages_ff_reg* is considered, and not the usual dest_hsdata_ff_reg*, but should use the same reasoning. For reference, dest_clk_period = 2.5ns, so the max bus_skew is set to 4x2.5ns, as well as the set_max_delay -datapath_only.

 

According to the explanation, the set_bus_skew analyses the skew between capture times (destination FF) of all bus paths.

 

To calculate this "capture time", I would think that Vivado accounts for:

 

  1. net_delay (datapath_only) delta between bus paths
  2. clock skew between destination FFs (not the usual source -> destination clock skew)

Therefore, what I think they are trying to constrain is the clock_skew delta, because the max_net_delay delta is already 10ns (set_max_delay ... 4*2.5 -datapath_only).

 

A violation scenario where dest_hsdata_ff_reg[1] is close to sample old data:

 

  1. net_delay(src_hsdata_ff_reg[0] -> dest_hsdata_ff_reg[0]) ≃ 0ns
  2. net_delay(src_hsdata_ff_reg[1] -> dest_hsdata_ff_reg[1]) ≃ 10ns
  3. clock_skew_delta(dest_hsdata_ff_reg[1], dest_hsdata_ff_reg[0]) > 0ns, (positive indicates clk in [1] arrives later than [0])

Would be prevented by the set_bus_skew, however:

 

  1. net_delay(src_hsdata_ff_reg[0] -> dest_hsdata_ff_reg[0]) ≃ 5ns
  2. net_delay(src_hsdata_ff_reg[1] -> dest_hsdata_ff_reg[1]) ≃ 10ns
  3. clock_skew_delta(dest_hsdata_ff_reg[1], dest_hsdata_ff_reg[0]) > 0ns, (positive indicates clk in [1] arrives later than [0])

Would not be reasonably caught by the set_bus_skew constraint, but may still have problems with dest_hsdata_ff_reg[1].

 

What I am not doing wrong in my set_bus_skew analysis?

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