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Observer kg1
Observer
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Registered: ‎04-03-2016

AXI4-Stream Data FIFO using UltraRAM Ultrascale+

Hi,

The AXI4-Stream Infrastructure IP Suite (PG085) v3.0 states that the AXI4-Stream Data FIFO can be implement as Distributed RAM, Block RAM and UltraRAM (on select devices).

Can somebody indicate which devices support UltraRAM Data FIFO implementation and how this can be enabled? Since the GUI in the IPI does not offer a selection of memory primitives.

The FPGA I am working on is the XCZU7EV and the Vivado Version is 2017.4.

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