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Calculating SERDES Latency

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Visitor
Posts: 18
Registered: ‎04-21-2017

Calculating SERDES Latency

Dear Colleagues,

 

I need to calculate the latency of a Virtex-7 Ultrascale GTH serdes when setup as follows.

 

"32-bit direct PMA output (no PCS/MAC) running at 10G".

 

I have found Latency data on both GTH and GTY serdes in AR66341 and AR64309, but I don't know how to manipulate this data to answer the question at hand.

 

Any help would be appreciated.

 

Regards,

 

DJE666

Moderator
Posts: 2,257
Registered: ‎02-16-2010

Re: Calculating SERDES Latency

What difficulty are you facing in calculating the latency? The AR provides comments to help with calculating the latency.
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Moderator
Posts: 1,654
Registered: ‎02-14-2014

Re: Calculating SERDES Latency

Hello @dje666,

 

The appropriate way to manipulate this latency would be simulating example design and checking latency from TXDATA to RXDATA port. This should be within the range specified by these answer records. Let us know if there is any discrepancy in analysis/calculation.

Regards,
Ashish
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Mentor
Posts: 417
Registered: ‎12-03-2007

Re: Calculating SERDES Latency

@dje666 ,

 

One way to determine serdes latency for a specific configuration is to generate an IP core, example design, and run functional simulation.

 

Thanks,

Evgeni

Instructor
Posts: 3,546
Registered: ‎01-23-2009

Re: Calculating SERDES Latency

One way to determine serdes latency for a specific configuration is to generate an IP core, example design, and run functional simulation.

 

I have to disagree (or at least partially disagree).

 

First - let's be clear - we are talking about a GTH, not a SERDES. The FPGA have ISERDES/OSERDES blocks for conventional serialization and deserialization. For these, you can (at least partly) use simulation to understand their behavior. But the OP specifically says the GTH here - this is not an ISERDES/OSERDES.

 

For the GTH, the simulation model is merely a behavioral simulation of what is essentially an analog block. The full behavior of the extremely high speed clocks within the GTH, the clock crossing, the CDR, etc... are only "grossly" modeled for simulation purposes. Furthermore, particularly when it comes to latency, this is not completely deterministic - it has to do with the bring-up and synchronization of the various parts of the GTH. The single value given in a simulation will (at best) only be one possible answer from a range, or even (at worst) not even representative of that range (since, again, the GTH simulation model is only a behavioral model).

 

The only way to understand the latency of the GTH is to read the user guide, which documents the factors that contribute to the latency of the GTH transmitter and receiver. This will give you a range. And, beware, this range isn't "small" - if my memory serves me, the variation can be a good number of user clock periods.

 

Avrum

Visitor
Posts: 18
Registered: ‎04-21-2017

Re: Calculating SERDES Latency

Hi Venkata,

 

Thanks for getting back to me. The main issue I have is that whilst there is a massive amount of data in the AR's, I don't know which values are relevant to the configuration that I have proposed. If I can work out what values I should be using, then I can start to manipulate them.

 

DJE666