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Visitor murali@1996
Visitor
247 Views
Registered: ‎10-03-2018

Camera Link Receiver

Hiiiii,

      in VIVADO, for Serial IO ip, the Camera link Transmitter and Receiver Selection is Availbale upto 7 Series FPGA, and if I Select the Ultrascale Device, the Available option in the Serializer is only 4,8 bit. and No Specific interface related Selection Like 7 series Device...?

Why....????

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5 Replies
Scholar watari
Scholar
238 Views
Registered: ‎06-16-2013

Re: Camera Link Receiver

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Moderator
Moderator
233 Views
Registered: ‎08-08-2017

Re: Camera Link Receiver

Hi murali@1996

We have High speed SelectIO Wizard IP for the Ultrascale and Ultrascale+  devices which creates RTL that contains IO and clocking Logic such as 

RX/TX Bitslice control and PLL blocks customized to the user interface requirements.

RX_TX_Bitslice, RX_bitslice and TX_Bitslice are the native primitives for US/US+ architecture and gets instantiated/configured according to the HSSIO IP settings.

In short this is totally different IP . The SelectIO wizard Utilizes IODELAY and IOSERDES  Primitives which are Component mode Primitives in US/US+ devices.

Component mode in the sense , they are created primitives from RX_TX_bitslices.

We have Application note which utilizes Component mode primitives to construct LVDS Source Synchronous 7:1 Serialization and Deserialization interfaces which  are widely used in consumer devices such as televisions and Blu-ray players for video processing when passing data between components

https://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf

Alternatively as there is no ready template for camera link receiver when using HSSIO IP, you need to analyse the interface detailing (Clocking, data rate, No of pins ) and configured HSSIO IP accordingly.

 

 

 

 

 

 

 

 

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Visitor murali@1996
Visitor
182 Views
Registered: ‎10-03-2018

Re: Camera Link Receiver

Dear @watari

Yes,

I referred and I did the implementation also. whenever I am adding those 7:1 files to the design, the Remaining global clocks not showing in Debug search to take debug window. once the serdes macro is commented, again the expected clocks are available in debug window....

I am going to use that serdes that you have provided. in parallel i am looking for alternate solutions also.....

Thanks and regards

Murali

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Scholar watari
Scholar
178 Views
Registered: ‎06-16-2013

Re: Camera Link Receiver

Hi murali@1996

 

Could you explan your target frequency ?

It might be PLL range issue...

 

Best regards,

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Visitor murali@1996
Visitor
176 Views
Registered: ‎10-03-2018

Re: Camera Link Receiver

hi @watari

Now am in implementation stage only, not yet connected with hardware. The camera link frame clock speed is from 25 to 85MHz, i am going start with 25MHz.

regards 

Murali M

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