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Visitor jdyke
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Registered: ‎06-26-2019

Compatible Signaling Standards

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On the same FPGA HP Bank I am going to supply it with 1.2V and the VREF with 0.6V. Would I be able to use some pins at the LVCMOS12 standard and some pins at the HSUL_12_DCI standard or is there an issue since HSUL_12_DCI needs an 0.6V VREF where as the LVCMOS12 does not need a VREF?

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Registered: ‎01-22-2015

Re: Compatible Signaling Standards

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@jdyke 

    Would I be able to use some pins at the LVCMOS12 standard and some pins at the HSUL_12_DCI standard...?
Yes, for UltraScale, because:

  • both are available in HP banks
  • both require the same VCCO=1.2V for input and output
  • there is no conflicting need for VREF (ie. LVCMOS12 does not use VREF, and HSUL_12_DCI needs VREF=0.60V)

For more information, see the section surrounding Table 1-77 in Xilinx document UG571.

-and if you accidentally choose incompatible standards, the Vivado tools should warn you.

Mark

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218 Views
Registered: ‎01-22-2015

Re: Compatible Signaling Standards

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@jdyke 

    Would I be able to use some pins at the LVCMOS12 standard and some pins at the HSUL_12_DCI standard...?
Yes, for UltraScale, because:

  • both are available in HP banks
  • both require the same VCCO=1.2V for input and output
  • there is no conflicting need for VREF (ie. LVCMOS12 does not use VREF, and HSUL_12_DCI needs VREF=0.60V)

For more information, see the section surrounding Table 1-77 in Xilinx document UG571.

-and if you accidentally choose incompatible standards, the Vivado tools should warn you.

Mark

Visitor jdyke
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204 Views
Registered: ‎06-26-2019

Re: Compatible Signaling Standards

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Hello  markg@prosensing.com ,

 

Thank you for your answer. I ask as I am designing an FMC card for an Ultrascale FPGA and by the time I am looking in the Vivado tool it would be too late!

I am not sure if i should post another question or just piggyback off of this question but, the 1.2V that I am supplying to the FPGA Bank in question, can I use a voltage divider between the 1.2V rail and ground with two 20Kohm resistors in series and just tap the 0.6V there as my VREF? or should I use an LDO and convert the voltage from 1.2V to 0.6V for VREF?

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Registered: ‎01-22-2015

Re: Compatible Signaling Standards

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@jdyke 

      I am not sure if i should post another question or just piggyback off of this question…
After a thread is marked answered, the people-with-answers don't usually look at it.  So, if I couldn't help with your follow-on question then you might be stuck. 

     ...about VREF:
On page-22 and page-68 of UG571, it is explained that some banks can generate the INTERNAL_VREF (which is the 0.6V that you mention) using VCCO.  Thus, the externally-applied VREF is sometimes not needed (but VREF pin must be properly terminated).  Where the VREF input must be supplied, I'm not sure what design to recommend.  <Here> is a thread with good info.  

     …about powering UltraScale:
It is a challenge!  Be sure to get the specific datasheet for your device and pay particular attention to “Power-On/Off Power Supply Sequencing”,  “Power-on Current by Device”, and “Power Supply Ramp Time”.  Schematics and parts lists are freely available for UltraScale Boards offered by Xilinx.  Looking at the power-supply design on these boards (eg. KC705) will give you some ideas.  

     …by the time I am looking in the Vivado tool it would be too late!
Please look at Chapter 2, “Board and Device Planning”, of UG949.  You can get in trouble with these advanced FPGAs if you don't use Vivado to do some I/O planning (and other planning) during board design.

Cheers,
Mark

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