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Visitor zjywindwalk
Visitor
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Registered: ‎12-29-2018

FDCE post implemetation simulation failed

Ref to the attachment, 

Q_reg_1 is the Q output of FDCE,

Q_i_1_n_0 is the D input,

CPU_CCLK is the clock.

Functional simulation works correctly.

No timing violation is reported related to the above FDCE.

During my post implementation simulation, FDCE fails to capture the D input, why?

And the actual result is not right, either.

The tool is vivado/2017.4

 

Thanks in advance,

Jevon

IMG_20190212_154455.jpg
IMG_20190212_104930.jpg
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