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110 Views
Registered: ‎07-23-2019

GTH jitter

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I'm using a programmable clock generator with low jitter, apparently valid for 10 GbE, and this will be the reference (not fixed yet, probably between 100 - 200 MHz) for a 2 GHz transceiver using the Ultrascale+ GTH. 

The question is, how does the reference jitter relate to the i/o?

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73 Views
Registered: ‎09-17-2018

Re: GTH jitter

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Nope,

The PLL attenuates some jitter above the PLL loop pole filter frequency, so start with jitter less than the requirement, and then measure it.  Your power supplies add to jitter, along with any cross-talk, ground bounce, vcc bounce.  In essense, anything less than perfect adds jitter.  It is called signal integrity engineering, so you may need to hire one (or go back to school and learn about it).

l.e.o

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94 Views
Registered: ‎09-17-2018

Re: GTH jitter

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Clock jitter closes the eye pattern in the time axis,

Which increases the bit error rate.  Most serial standards have jitter requirements (not to be exceeded), so more jitter may mean you fail a compliance test (even if you have no errors).

l.e.o.

 

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81 Views
Registered: ‎07-23-2019

Re: GTH jitter

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Thanks. Sure, but my specific question is:

I'm supplying my GTH with a reference clock of N MHz and X ps jitter. My spec for 2 GHz input/output is to be less than Y ps jitter. 

What equation/ relation is there between X and Y?

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74 Views
Registered: ‎09-17-2018

Re: GTH jitter

Jump to solution

Nope,

The PLL attenuates some jitter above the PLL loop pole filter frequency, so start with jitter less than the requirement, and then measure it.  Your power supplies add to jitter, along with any cross-talk, ground bounce, vcc bounce.  In essense, anything less than perfect adds jitter.  It is called signal integrity engineering, so you may need to hire one (or go back to school and learn about it).

l.e.o

61 Views
Registered: ‎07-23-2019

Re: GTH jitter

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@lowearthorbit   well, I feel I never left Uni, always learning, sometimes the nice way, sometimes the other...

Part of the problem is that both the board and clock gen are already there, so I don't even have the PCB files to kick Hyperlynx... true that jitter depends on supply noise as well, and that in turn depends on what's running on them and not even the board maker will have such data.

So I think the shortest path, in this case, is to find it empirically, there is no point in spending time analyzing something that can 'just' be turned on and checked on the scope. 

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