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HS SelectIO: how to release RX_CLK

Accepted Solution Solved
Explorer
Posts: 100
Registered: ‎01-18-2011
Accepted Solution

HS SelectIO: how to release RX_CLK

[ Edited ]

Hello,

 

It is written in the UG571: "If you have control of the TX while the RX is coming out of reset, the CLK to the RX side should be stopped until the RX VTC_RDY signal is asserted" - i.e. RX_CLK appears after RX VTC_RDY signal is asserted.

 

It is written in the PG188: "When any pin is enabled as Clock Forward, it is mandatory to hold the counterpart design (RX) in reset until the TX is out of reset and rst_seq_done of TX is asserted. This will ensure a reliable clock to the RX" - i.e. RX_CLK appears before RX VTC_RDY signal is asserted.

 

It seems to me that these quotes contradict each other. When it is necessary to release RX_CLK actually?

 


Accepted Solutions
Highlighted
Community Manager
Posts: 259
Registered: ‎08-08-2007

Re: HS SelectIO: how to release RX_CLK

Hi @taganrog,

 

If the FPGA is forwarding the Clock it is mandatory to hold the RX in reset until the TX out of the FPGA is asserted.

If the FPGA is the RX we recommend that you stop capture RX_CLK until the RDY is asserted otherwise the inputs may not be aligned to each other : https://www.xilinx.com/support/answers/66244.html

If its FPGA to FPGA then these do contradict each other but the Mandatory requirement of holding the RX in Reset take precedence. If its FPGA to FPGA and you require alignment between channels then you will need to use the Bitslipping functionality to ensure alignment.  

 

 

 

 

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Highlighted
Community Manager
Posts: 259
Registered: ‎08-08-2007

Re: HS SelectIO: how to release RX_CLK

Hi @taganrog,

 

If the FPGA is forwarding the Clock it is mandatory to hold the RX in reset until the TX out of the FPGA is asserted.

If the FPGA is the RX we recommend that you stop capture RX_CLK until the RDY is asserted otherwise the inputs may not be aligned to each other : https://www.xilinx.com/support/answers/66244.html

If its FPGA to FPGA then these do contradict each other but the Mandatory requirement of holding the RX in Reset take precedence. If its FPGA to FPGA and you require alignment between channels then you will need to use the Bitslipping functionality to ensure alignment.  

 

 

 

 

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Don’t forget to reply, kudo, and accept as solution.
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