UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
828 Views
Registered: ‎04-16-2018

Issue about IDELAY3 drivers

[DRC REQP-1741] IDELAYE3 drives invalid load: IDELAYE3 i_if_a/i_adc_clk/i_rx_data_idelay DATAOUT pin (net: i_if_a/i_adc_clk/clk_idelay_s) may not drive a BUFG*.

 

 

module ad_data_clk
  (

  input               rst,
  output              locked,
  input               delay_clk,
  input               clk_in_p,
  input               clk_in_n,
  input [8:0]         delay_value,
  output              clk_ibufg_s
  );


  wire                clk_ibuf_s;
  wire                clk_idelay_s;
  // defaults

  assign locked = 1'b1;

  IBUFGDS i_rx_clk_ibuf (
    .I (clk_in_p),
    .IB (clk_in_n),
    .O (clk_ibuf_s));

   BUFG i_clk_gbuf (
     .I (clk_idelay_s),
     .O (clk_ibufg_s));

   // (* IODELAY_GROUP = IODELAY_GROUP *)
     IDELAYE3 #(
      .CASCADE("NONE"),          // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
      .DELAY_FORMAT("COUNT"),     // Units of the DELAY_VALUE (COUNT, TIME)
      .DELAY_SRC("IDATAIN"),     // Delay input (DATAIN, IDATAIN)
      .DELAY_TYPE("VAR_LOAD"),      // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
      .DELAY_VALUE(0),           // Input delay value setting
      .IS_CLK_INVERTED(1'b0),    // Optional inversion for CLK
      .IS_RST_INVERTED(1'b0),    // Optional inversion for RST
      .REFCLK_FREQUENCY(200.0),  // IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
      .SIM_DEVICE("ULTRASCALE_PLUS")//, // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
                                 // ULTRASCALE_PLUS_ES2)
      // .UPDATE_MODE("ASYNC")      // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
   )
   i_rx_data_idelay (
      .CASC_OUT(),       // 1-bit output: Cascade delay output to ODELAY input cascade
      .CNTVALUEOUT(), // 9-bit output: Counter value output
      .DATAOUT(clk_idelay_s),         // 1-bit output: Delayed data output
      .CASC_IN(1'b0),         // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
      .CASC_RETURN(1'b0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
      .CE(1'b0),                   // 1-bit input: Active high enable increment/decrement input
      .CLK(delay_clk),                 // 1-bit input: Clock input
      .CNTVALUEIN(delay_value),   // 9-bit input: Counter value input
      .DATAIN(1'b0),           // 1-bit input: Data input from the logic
      .EN_VTC(1'b0),           // 1-bit input: Keep delay constant over VT
      .IDATAIN(clk_ibuf_s),         // 1-bit input: Data input from the IOBUF
      .INC(1'b0),                 // 1-bit input: Increment / Decrement tap delay input
      .LOAD(1'b1),               // 1-bit input: Load DELAY_VALUE input
      .RST(1'b0)                  // 1-bit input: Asynchronous Reset to the DELAY_VALUE
   );
   
endmodule

Tags (1)
0 Kudos
1 Reply
Moderator
Moderator
811 Views
Registered: ‎08-08-2017

Re: Issue about IDELAY3 drivers

Hi @kuailelinghun

 

Looking at the shared RTL, your objective here is the delay the clock. But IDELAYE3 is not used for Clock Delaying.

 

idelay.PNG

 https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf   (page 167).

 

------------------------------------------------------------------------------------------------------------------------------------------------------

Please reply if you have any further queries, Give Kudos and accept as solution if you get one

-------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos