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Explorer
Explorer
159 Views
Registered: ‎04-11-2016

ODELAY Example design

Hi,

Is there any example design for ODELAY primitive  (in Ultrascale ODELAYE3 and in 7 Series ODELAYE2)  implemented in HP bank?

Regards

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Scholar dpaul24
Scholar
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Registered: ‎08-07-2014

Re: ODELAY Example design

@fpgalearner,

I don't think so. It is not a complicated primitive.

If you want to play around, just implement a counter and have two output ports from it. In one of them put this ODELAY. Then you can compare in sim how the ODELAYed-output varies from the normal counter output.

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Highlighted
132 Views
Registered: ‎01-22-2015

Re: ODELAY Example design

@fpgalearner 

When designing an FPGA IO interface it is the goal to have the  capture edge of the IO clock located in the middle of the IO data-eye.  To achieve this goal, we sometimes use the ODELAY primitive to delay (ie. time shift) the IO data with respect to the IO clock.

I suggest that you start your ODELAY learning with the simpler ODELAYE2 that can be easily instantiated into your design as shown in UG953, and then used as described in UG471.

You’ll find an example design that uses ODELAYE2 at the following site.

https://wiki.analog.com/resources/fpga/docs/ssd_if

However, instead of using ODELAY to delay the IO data, we often use an MMCM to delay/shift the IO clock - which can be easier, too.

Mark