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Explorer
Explorer
563 Views
Registered: ‎01-18-2011

PHY_RDEN failed timing

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Hello,

 

UG571: " RXTX_BITSLICE receivers or RX_BITSLICEs require that the PHY_RDEN[3:0] inputs of the BITSLICE_CONTROL are pulled High. Use the VTC_RDY signal and a two register synchronizer running from the application clock to perform this action."

 

PHY_RDEN are synchronous to the application clock = PLL0.CLKOUT0 in the my design. PLL0 is located in the same bank. But I have many timing setup errors for PHY_RDEN signals. Worst negative slack is -1.839 ps. Destination clock is BITSLICE_CONTROL.phy_clk_DIV, not application clock. Frequency of the PLL0.CLKOUT0 is 250 MHz. Frequency of the PLL0.CLKOUTPHY clock is 1000 MHz.

 

What is the reason for such serious setup timing errors?


 

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Explorer
Explorer
785 Views
Registered: ‎01-18-2011

Re: PHY_RDEN failed timing

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See AR# 67104 "High Speed SelectIO Wizard - Timing violations can be seen on the CLKOUT0 of the PLL".

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Explorer
Explorer
786 Views
Registered: ‎01-18-2011

Re: PHY_RDEN failed timing

Jump to solution

See AR# 67104 "High Speed SelectIO Wizard - Timing violations can be seen on the CLKOUT0 of the PLL".

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