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Visitor lbaischer
Visitor
277 Views
Registered: ‎05-26-2018

Placing PLL in clock region of bank 64 of XCZU9EG-ffvc900-1-e is not possible

I try to implement a PLL in the clock region X370 of bank 64 to capture an external input clock.
The problem is now that at the implementation I get an error that it is not possible to place a PLL in a high density I/O bank. But bank 64 is an high performance bank and at the device view it is visible that there is an available PLL at this bank.  

The input clock is using LVDS as I/O standard.
The positive clock signal is placed at pin AF6. 

If I use the CLOCK_DEDICATED_ROUTE constraint which is recommended by Vivado the PLL is placed in another bank.  

Is it possible to set the placement of the PLL manually to PLL_X0Y0 or to PLL_X0Y1 or can you please explain me why it is not possible to place the PLL in this clocking ?

Error message:

[Place 30-899] Unroutable Placement - The Input buffer driving a PLL clock input needs to be in the same clock region as the PLL or driving an appropriate Clock buffer for the PLL clock input. If the I/O is locked to HIGH_DENSITY IO banks, please review and update the LOC constraints or insert a BUFGCE instance in between as I/O driving PLL can not be placed in HIGH_DENSITY IO banks. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/clk_wiz_0/inst/clkin1_ibufds/O] >

design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y32
design_1_i/clk_wiz_0/inst/plle4_adv_inst (PLLE4_ADV.CLKIN) is provisionally placed by clockplacer on PLL_X0Y5

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_pll_bufg
Status: PASS
Rule Description: A PLL driving a BUFG must be placed in the same clock region of the device as the
BUFG
design_1_i/clk_wiz_0/inst/plle4_adv_inst (PLLE4_ADV.CLKOUT0) is provisionally placed by clockplacer on PLL_X0Y5
design_1_i/clk_wiz_0/inst/clkout1_buf (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y52

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and design_1_i/clk_wiz_0/inst/clkout1_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y52

 

Thanks,

Lukas

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2 Replies
Moderator
Moderator
251 Views
Registered: ‎08-08-2017

Re: Placing PLL in clock region of bank 64 of XCZU9EG-ffvc900-1-e is not possible

Hi @lbaischer

Yes the  bank 64 of XCZU9EG-ffvc900-1-e is high performance bank and AF6 is clock capable pin (QBC) and can drive PLL/MMCM.

As you know the a CMT contains one mixed-mode clock manager (MMCM) and two phase-locked loops (PLLs).

Capture.PNG

can you once check if these two PLLs are not driven by other GC/QBC pins in the bank64?

If not can you sent us (Privately or Publicly ) the .dcp file to further lookn into this issue.

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Visitor lbaischer
Visitor
236 Views
Registered: ‎05-26-2018

Re: Placing PLL in clock region of bank 64 of XCZU9EG-ffvc900-1-e is not possible

This is the only PLL I am using at the moment, therefore these two PLL should not be driven by another signal. 

If I change the clock pin to a GC clock pin one of these two PLLs is used. Therefore the issue seems to be that I am using a QBC clock pin. Unfortunately in my case I have to use the pin AF6 as input clock pin, so this is not a feasible solution.

As requested by you, I attached the dcp file. 

Thanks,

Lukas

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