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Contributor
Contributor
359 Views
Registered: ‎04-01-2015

RF ADC Multi-Tile Synchronization Intermittent Failure

I'm having troubles getting multi-tile ADC synchronization to work reliably on ZCU111 startup.  

Here's the code I'm using at startup (NTILES is 3).

 

void
rfADCsync(void)
{
    int tile;
    XRFdc_IPStatus IPStatus;
    XRFdc_MultiConverter_Sync_Config Config;

    if (XRFdc_GetIPStatus(&rfADC, &IPStatus) != 0) {
        printf("Can't get IP status.\n");
        return;
    }
    XRFdc_MultiConverter_Init(&Config, NULL, NULL);
    for (tile = 0 ; tile < NTILES ; tile++) {
        if (IPStatus.ADCTileStatus[tile].IsEnabled) {
            Config.Tiles |= 1 << tile;
        }
    }
    syncStatus = XRFdc_MultiConverter_Sync(&rfADC, XRFDC_ADC_TILE, &Config);
    if (syncStatus != XRFDC_MTS_OK) {
        fatal("XRFdc_MultiConverter_Sync failed: %d", syncStatus);
        return;
    }
    printf("ADC synchronization complete:\n");
    for (tile = 0 ; tile < NTILES ; tile++) {
        if (Config.Tiles & (1 << tile)) {
            uint32_t factor;
            XRFdc_GetDecimationFactor(&rfADC, tile, 0, &factor);
            printf("  ADC %d: Latency(T1)=%d, Adjusted Delay Offset(T%d)=%d\n",
                        tile, Config.Latency[tile], factor, Config.Offset[tile]);
        }
    }
}

 

 

Somes this succeeds as follows:

DTC Scan PLL
Target 64, DTC Code 20, Diff 44, Min 44
RefTile (0): DTC Code Target 64, Picked 20
ADC0: 22000111113333222200*0011333333223000013333333223220010133333322#000103133333320021010013333222000211113313332202000013131333232
Tile (1): Max/Min 20/20, Range 0
Tile (1): Code 85, New-Range: 65, Min-Range: 65
Tile (1): Code 85, Range Prev 0, New 65
ADC1: 33320000111013333322#0000111133333322000011133323332222101113333332200001031333333300*000113333222200010111333333222000111133333
Tile (2): Max/Min 85/20, Range 65
Tile (2): Code 93, New-Range: 73, Min-Range: 73
Tile (2): Code 125, New-Range: 105, Min-Range: 73
Tile (2): Code 93, Range Prev 65, New 73
ADC2: 02011133333222200011#333333232200111133332222020011331333322200001011333332220201001333332200*0011111323332200011311333332200000

DTC Scan T1
Target 64, DTC Code 7, Diff 57, Min 57
Target 64, DTC Code 48, Diff 16, Min 16
Target 64, DTC Code 94, Diff 30, Min 16
RefTile (0): DTC Code Target 64, Picked 48
ADC0: 000000000000000011133313333222220200000000000000*000000000000000#313333333332020000000000000000000000000000000011133333332222200
Tile (1): Max/Min 48/48, Range 0
Tile (1): Code 18, New-Range: 30, Min-Range: 30
Tile (1): Code 65, New-Range: 17, Min-Range: 17
Tile (1): Code 113, New-Range: 65, Min-Range: 17
Tile (1): Code 65, Range Prev 0, New 17
ADC1: 222200000000000000000000000000000010113133333232#2200000000000000*00000000000000111011133333322322200000000000000000000000000000
Tile (2): Max/Min 65/48, Range 17
Tile (2): Code 25, New-Range: 40, Min-Range: 40
Tile (2): Code 73, New-Range: 25, Min-Range: 25
Tile (2): Code 117, New-Range: 69, Min-Range: 25
Tile (2): Code 73, Range Prev 17, New 25
ADC2: 333333323200000000000000000000000000000001000111#332222222220000000000000*000000000000001111113333332322022000000000000000000000
Marker Read Tile 0, FIFO 0 - 00014000 = 100024: count=36, loc=0,done=1
ADC0: Marker: - 36, 0
Marker Read Tile 1, FIFO 0 - 00018000 = 100024: count=36, loc=0,done=1
ADC1: Marker: - 36, 0
Marker Read Tile 2, FIFO 0 - 0001C000 = 100024: count=36, loc=0,done=1
ADC2: Marker: - 36, 0
Count_w 8, loc_w 1
SysRef period in terms of ADC T1s = 512
ADC target latency = 288
Tile 0, latency 288, max 288
Tile 1, latency 288, max 288
Tile 2, latency 288, max 288
Target 288, Tile 0, delta 0, i/f_part 0/0, offset 0
Target 288, Tile 1, delta 0, i/f_part 0/0, offset 0
Target 288, Tile 2, delta 0, i/f_part 0/0, offset 0
ADC synchronization complete:
  ADC 0: Latency(T1)=288, Adjusted Delay Offset(T1)=0
  ADC 1: Latency(T1)=288, Adjusted Delay Offset(T1)=0
  ADC 2: Latency(T1)=288, Adjusted Delay Offset(T1)=0

 

 

But about half the time it fails with:

DTC Scan PLL
Target 64, DTC Code 58, Diff 6, Min 6
RefTile (0): DTC Code Target 64, Picked 58
ADC0: 1133333020201133133333223020013333333220220001113333333200*00133#333322322001133333232220011133333332222000131133332322220000111
Tile (1): Max/Min 58/58, Range 0
Tile (1): Code -1, Range Prev 0, New 128
ADC1: 1133333333330000111133332333200011133333332220011113333323#233200133333222220011113333333222201010333332223200111131333332020001
Unable to capture analog SysRef safely on ADC tile 1
Tile (2): Max/Min 58/58, Range 0
Tile (2): Code -1, Range Prev 0, New 128
ADC2: 0011331331332202001133333322222200033333333322200011333333#222201111333332222011110113333222000131133333332202000133333333000200
Unable to capture analog SysRef safely on ADC tile 2

DTC Scan T1
Target 64, DTC Code 38, Diff 26, Min 26
Target 64, DTC Code 88, Diff 24, Min 24
Target 64, DTC Code 122, Diff 58, Min 24
RefTile (0): DTC Code Target 64, Picked 88
ADC0: 0000001011113333322222200000000000000000000000000000000101311333#33322200200000000000000*000000000000001133133332223200000000000
Tile (1): Max/Min 88/88, Range 0
Tile (1): Code 13, New-Range: 75, Min-Range: 75
Tile (1): Code 56, New-Range: 32, Min-Range: 32
Tile (1): Code 106, New-Range: 18, Min-Range: 18
Tile (1): Code 106, Range Prev 0, New 18
ADC1: 0000000000000000000000000001111131333232220000000000000000000000000000001000111133333223#22200000000000000*000000000000000111313
Tile (2): Max/Min 106/88, Range 18
Tile (2): Code 12, New-Range: 94, Min-Range: 94
Tile (2): Code 56, New-Range: 50, Min-Range: 50
Tile (2): Code 104, New-Range: 18, Min-Range: 18
Tile (2): Code 104, Range Prev 18, New 18
ADC2: 0000000000000000000000000110011313333322200000000000000000000000000000000111331333333222#000000000000000*00000000000000001011333
Marker Read Tile 0, FIFO 0 - 00014000 = 10003C: count=60, loc=0,done=1
ADC0: Marker: - 60, 0
Marker Read Tile 1, FIFO 0 - 00018000 = 10003C: count=60, loc=0,done=1
ADC1: Marker: - 60, 0
Marker Read Tile 2, FIFO 0 - 0001C000 = 10003C: count=60, loc=0,done=1
ADC2: Marker: - 60, 0
Count_w 8, loc_w 1
SysRef period in terms of ADC T1s = 512
ADC target latency = 480
Tile 0, latency 480, max 480
Tile 1, latency 480, max 480
Tile 2, latency 480, max 480
Target 480, Tile 0, delta 0, i/f_part 0/0, offset 0
Target 480, Tile 1, delta 0, i/f_part 0/0, offset 0
Target 480, Tile 2, delta 0, i/f_part 0/0, offset 0
*** Fatal error: XRFdc_MultiConverter_Sync failed: 128

I'm providing about a tenth of a second delay from the programming of the RF clock synthesizers until initializing the data converters:

void
rfADCinit(void)
{
    int i;
    XRFdc_Config *configp;
    
    metal_set_log_handler(myLogHandler);
    metal_set_log_level(METAL_LOG_DEBUG);

    configp = XRFdc_LookupConfig(XPAR_XRFDC_0_DEVICE_ID);
    if (!configp) fatal("XRFdc_LookupConfig");
    i = XRFdc_CfgInitialize(&rfADC, configp);
    if (i != XST_SUCCESS) fatal("XRFdc_CfgInitialize=%d\n", i);
    XRFdc_StartUp(&rfADC, XRFDC_ADC_TILE, -1);
}

and then about another tenth of second delay before invoking the ADC synchronization code shown above.  

Is there something I'm missing or is this expected behaviour?

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21 Replies
Moderator
Moderator
299 Views
Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Is this the ZCU111 set up? If so can you try the 8x8 MTS design we provide... 

It looks like it can't find a stable point in the VCO frequency of the PLL to position the sysref in. 

It needs to do this reliably. to me it looks like your capture point jumps all over the place between tiles and between runs. If you look at the # this is the start point in the dtc and the * is where it ends up. then the next tile it starts where it found it in the previous tile. But it seems to jump from one end of the delay line to the next every other tile. 

Are you following all the rules about the SYSREF as discussed in the docs? What is the frequency of everything here?

Are you sure that you are getting stable clocks always? Are you sure the SYSREF itself is reliable?

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Contributor
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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Thanks for the reply.  Here are the screen grabs showing how I used the TI tools to configure the RF ADC clock generation components.  The actual sampling clock is generated inside the FPGA using the internal PLL as an 8x multiplier.  So the sampling frequency is 3.99712 GHz and the SYSREF frequency is 7.806875 MHz.  From my reading of the documentation these values are aceptable.    And about half the time it does the synchronization without complaint.

I've also attached a screen shot showing how I generate the SYSREF sampling clock (62.455 MHz) and ADC AXI MASTER clock (499.64 MHz) using an MMCM block.

I used these two clocks to latch the SYSREF signal as shown in the documentation:

/////////////////////////////////////////////////////////////////////////////
// Generate tile synchronization user_sysref_adc
// As shown in PG269 (v2.0) Zynq UltraScale+ RFSoC RF Data Converter
//   Figure 78: Example Fabric SYSREF Capture
//   Figure 80: Example Fabric SYSREF Capture for Different Clock Rates
// Two stage sampling:
//   First stage at FPGA_REFCLK_OUT_C rate (62.455 MHz)
//   Second stage at ADC AXI rate (499.64 MHz)
// Buffer SYSREF_FPGA_C onto a clock line so its frequency can be monitored.
wire sysrefRaw;
(*ASYNC_REG="TRUE"*) reg sysrefSampled, user_sysref_adc;
IBUFDS sysrefBuf(.I(SYSREF_FPGA_C_P), .IB(SYSREF_FPGA_C_N), .O(sysrefRaw));
BUFG sysrefBG(.I(sysrefRaw), .O(sysrefClk));
always @(posedge adcSysrefSamplingClk) begin
    sysrefSampled <= sysrefRaw;
end
always @(posedge adcClk) begin
    user_sysref_adc <= sysrefSampled;
end

  LMK04208.pngLMK04208 -- Clock distribution modeLMK04208out.pngLMK04208 -- OutputsLMX2594.pngLMX2594 ConfigurationADCclks.pngSYSREF and ADC clock generation

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Moderator
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Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

The frequencies and the scheme in the fabric seem ok to me.
In the failing case it isn't getting as far are measuring the FIFO latency before it encounters a problem.
In this instance we can't seem to safe capture sysref in the Tile PLL so I wonder what can be going on here.
I will check on the clocks and also take a look at what the VCO might be running at in this case. maybe there is a limitation there.
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Contributor
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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Here's an example of the ADC configuration.  All four tiles are configured like this.

RFDC.pngExample ADC configuration

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Contributor
Contributor
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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Are the tile synchronization problems coming because I'm using the on-chip PLL to get the sampling clock?  I did this because I didn't feel that it was a good idea to run 4 GHz clock from the RF synthesizer to the FPGA.  Maybe that's acceptable, though.

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Moderator
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Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

using the tile PLL is more stringent on the sysref capture, but MTS will still work

is this a zcu111? creating a clock with the RF PLLs on the ZCU111 is fine.

Keith 

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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Yes, this is a ZCU111.

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Contributor
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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

To see if the multi-tile synchronization problems were associated with the RFDC internal PLL I reconfigured things to disable it.

Here's the ADC configuration:

Screen Shot 2019-05-03 at 10.28.38 AM.pngADC configuration (no RFDC PLL)

and here's the RF synthesizer configuration:

LMX2594.pngLMX2594 configuration (full speed ADC clock)

The RF synthesizer seems to be working -- here's what I read back during operation

       rb_VCO_SEL: 1
      rb_LD_VTUNE: Locked
   rb_VCO_CAPCTRL: 77
   rb_VCO_DACISET: 323
           OSC_2X: 1
             MULT: 1
            PLL_R: 1
        PLL_R_PRE: 1
            PLL_N: 64
          PLL_NUM: 0
          PLL_DEN: 1558
            CHDIV: 2
       CHDIV_DIV2: 0x1
          OUTA_PD: 0
          OUTB_PD: 0
Fphase_detector = Freference * 2
           Fvco = Freference * 128
            Frf = Freference * 64

And the RF ADC is putting out a clock -- here's the output from the frequency counters I built into the FPGA:

             ADC AXI clock: 499.639986
 ADC SYSREF sampling clock:  62.454999
          ADC SYSREF clock:   7.806874
             RF ADC0 clock:  31.227499

This all looks right to me.  But the ADC synchronization fails with complaints about no SYSREF

DTC Scan T1
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
Target 64, DTC Code 64, Diff 0, Min 0
RefTile (0): DTC Code Target 64, Picked 64
ADC0: 3000000000000000000000000000000000000000000000000000000000000000*000000000000000000000000000000000000000000000000000000000000000
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
Tile (1): Max/Min 64/64, Range 0
Tile (1): Code 64, New-Range: 0, Min-Range: 0
Tile (1): Code 64, Range Prev 0, New 0
ADC1: 3000000000000000000000000000000000000000000000000000000000000000*000000000000000000000000000000000000000000000000000000000000000
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
Tile (2): Max/Min 64/64, Range 0
Tile (2): Code 64, New-Range: 0, Min-Range: 0
Tile (2): Code 64, Range Prev 0, New 0
ADC2: 3000000000000000000000000000000000000000000000000000000000000000*000000000000000000000000000000000000000000000000000000000000000
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
Tile (3): Max/Min 64/64, Range 0
Tile (3): Code 64, New-Range: 0, Min-Range: 0
Tile (3): Code 64, Range Prev 0, New 0
ADC3: 3000000000000000000000000000000000000000000000000000000000000000*000000000000000000000000000000000000000000000000000000000000000
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
PL SysRef Timeout - PL SysRef not active: 1000
 in XRFdc_MTS_Sysref_Count
Marker Read Tile 0, FIFO 0 - 00014000 = F0000: count=0, loc=15,done=0
ADC0: Marker: - 0, 15
Analog SysRef timeout, SysRef not detected on ADC tile 0
Marker Read Tile 1, FIFO 0 - 00018000 = F0000: count=0, loc=15,done=0
ADC1: Marker: - 0, 15
Analog SysRef timeout, SysRef not detected on ADC tile 1
Marker Read Tile 2, FIFO 0 - 0001C000 = F0000: count=0, loc=15,done=0
ADC2: Marker: - 0, 15
Analog SysRef timeout, SysRef not detected on ADC tile 2
Marker Read Tile 3, FIFO 0 - 00020000 = F0000: count=0, loc=15,done=0
ADC3: Marker: - 0, 15
Analog SysRef timeout, SysRef not detected on ADC tile 3
Count_w 8, loc_w 1
Error : ADC SysRef frequency counter not yet done
ADC target latency = 15
Tile 0, latency 15, max 15
Tile 1, latency 15, max 15
Tile 2, latency 15, max 15
Tile 3, latency 15, max 15
Target 15, Tile 0, delta 0, i/f_part 0/0, offset 0
Target 15, Tile 1, delta 0, i/f_part 0/0, offset 0
Target 15, Tile 2, delta 0, i/f_part 0/0, offset 0
Target 15, Tile 3, delta 0, i/f_part 0/0, offset 0
*** Warning: XRFdc_MultiConverter_Sync failed: 4102

It complains about no PL SYSREF -- but as far as I can tell I do have this -- the frequency counter shows it.

I made no changes to the LMK04208 configuration.

Now I'm really confused.

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Contributor
Contributor
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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Missing PL SYSREF problem resolved.  Turned out that when I disabled the PLL in the RFDC wizard I also inadvertently unchecked the 'Enable Multi-Tile Sync'.  I turned it back on before the build above, but I didn't notice that the RFDC block had become disconnected from the input port providing the user_sysref_adc signal.  Restoring this connection got multi-tile synchronization working again. 

Multi-tile synchronization is now reliable.  I have rebooted the system dozens of times with no tile synchronization failures.  An example of the tile synchronization startup messages is show below.

So,

  1. What was it about using the RFDC internal PLL that caused the multi-tile synchronization to be unreliable?  I certainly didn't see anything in the documentation that indicated that this might be a problem
  2. What exactly is the purpose of the user_sysref_adc input to the RFDC block?  I understand the need for the differential external sysref_in port to allow synchronization across not just multiple tiles but also between multiple chips.  I don't understand the need nor purpose of the user_sysref_adc input, though.
DTC Scan T1
Target 64, DTC Code 23, Diff 41, Min 41
Target 64, DTC Code 69, Diff 5, Min 5
Target 64, DTC Code 114, Diff 50, Min 5
RefTile (0): DTC Code Target 64, Picked 69
ADC0: 3332200200000000000000000000000000000001111113333223200000000000#0000*0000000000000000110113333323222000000000000000000000000000
Tile (1): Max/Min 69/69, Range 0
Tile (1): Code 26, New-Range: 43, Min-Range: 43
Tile (1): Code 74, New-Range: 5, Min-Range: 5
Tile (1): Code 117, New-Range: 48, Min-Range: 5
Tile (1): Code 74, Range Prev 0, New 5
ADC1: 333332322220000000000000000000000000000000011131333333222022000000000#0000*00000000000000101111333333223220200000000000000000000
Tile (2): Max/Min 74/69, Range 5
Tile (2): Code 8, New-Range: 66, Min-Range: 66
Tile (2): Code 50, New-Range: 24, Min-Range: 24
Tile (2): Code 96, New-Range: 27, Min-Range: 24
Tile (2): Code 50, Range Prev 5, New 24
ADC2: 00000000000000000011113333332322220200000000000000*000000000000001001#3333333202220000000000000000000000000000001011113333332222
Tile (3): Max/Min 74/50, Range 24
Tile (3): Code 8, New-Range: 66, Min-Range: 66
Tile (3): Code 49, New-Range: 25, Min-Range: 25
Tile (3): Code 97, New-Range: 47, Min-Range: 25
Tile (3): Code 49, Range Prev 24, New 25
ADC3: 0000000000000000011111333333222220020000000000000*0000000000000011111#1333333322002000000000000000000000000000000111333323332220
Marker Read Tile 0, FIFO 0 - 00014000 = 100034: count=52, loc=0,done=1
ADC0: Marker: - 52, 0
Marker Read Tile 1, FIFO 0 - 00018000 = 100034: count=52, loc=0,done=1
ADC1: Marker: - 52, 0
Marker Read Tile 2, FIFO 0 - 0001C000 = 100034: count=52, loc=0,done=1
ADC2: Marker: - 52, 0
Marker Read Tile 3, FIFO 0 - 00020000 = 100034: count=52, loc=0,done=1
ADC3: Marker: - 52, 0
Count_w 8, loc_w 1
SysRef period in terms of ADC T1s = 512
ADC target latency = 416
Tile 0, latency 416, max 416
Tile 1, latency 416, max 416
Tile 2, latency 416, max 416
Tile 3, latency 416, max 416
Target 416, Tile 0, delta 0, i/f_part 0/0, offset 0
Target 416, Tile 1, delta 0, i/f_part 0/0, offset 0
Target 416, Tile 2, delta 0, i/f_part 0/0, offset 0
Target 416, Tile 3, delta 0, i/f_part 0/0, offset 0
ADC synchronization complete:
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Moderator
Moderator
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Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Safe capturing the tile sysref is the first part of MTS. This allows us to reset all the digital path clock dividers in the tiles so they all have the same phase. So now you have alignment inside all the tiles.

The problem now is that across tiles there is still the latency uncertainty of the dual clock FIFOs. This is the classic FIFO latency problem where you have the read and write enables asserted at different times. 

This is where the user or pl sysref comes in. We can use this to insert a marker bit into the fifo. 

So we use the incoming analog sysref in the DAC to start a counter.

The marker bit makes it's way through the fifo in each and stops the count.

Then we know the mismatch between the fifo. 

So sysref safe capture in the tile made more difficult when you have the pll. You need to safe capture too the vco frequency and the sample clock 

I want to take a closer look at the settings of your lmk and lmx in the case where you generate the reference input to the tile pll... 

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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Ah, now I see.  Thanks for the explanation.  The system is working great now that I am supplying the ADC sampling clock directly from the RF synthesizer.

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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

I can send the '.tcs' files produced by the TICS Pro application that shows all the register settings if you think that might help.

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Moderator
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Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

The Tics Pro file would be interesting. 

When you use the PLL in the tile you must safe capture it in the VCO frequency because you will need to align the phase the PLL output dividers.

I need to check up what could be happening here. 

Keith 

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Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Here are the .tcs files.  I had to add the .txt extension to get the web server to accept them.

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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Oops.  The lmx2594.tcs.txt file in my previous message is the configuration for the RFDC without the internal PLL (direct ADC sampling clock from LMX2594).  Here's the version I was using to provide the reference clock to the RFDC PLL.

 

 

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Re: RF ADC Multi-Tile Synchronization Intermittent Failure

O.K.  I think I understand the process now.  Here's my ADC synchronization code that does both tile and group syncrhonization:

void
rfADCsync(void)
{
    int tile, latency;
    XRFdc_IPStatus IPStatus;
    XRFdc_MultiConverter_Sync_Config Config;

    if (XRFdc_GetIPStatus(&rfADC, &IPStatus) != 0) {
        printf("Can't get IP status.\n");
        return;
    }
    XRFdc_MultiConverter_Init(&Config, NULL, NULL);
    for (tile = 0 ; tile < NTILES ; tile++) {
        if (IPStatus.ADCTileStatus[tile].IsEnabled) {
            Config.Tiles |= 1 << tile;
        }
    }

    /*
     * Synchronize between tiles in each group
     */
    syncStatus = XRFdc_MultiConverter_Sync(&rfADC, XRFDC_ADC_TILE, &Config);
    if (syncStatus != XRFDC_MTS_OK) {
        warn("XRFdc_MultiConverter_Sync (tiles) failed: %d", syncStatus);
        return;
    }

    /*
     * Synchronize between groups as described on page 113 of PG269 (v2.0)
     * "Zynq UltraScale+ RFSoC RF Data Converter", "Advanced Multi-Converter
     * Sync API Usage".
     */
    latency = -1;
    for (tile = 0 ; tile < NTILES ; tile++) {
        if (Config.Latency[tile] > latency) {
            latency = Config.Latency[tile];
        }
    }
    Config.Target_Latency = latency + 8;
    syncStatus = XRFdc_MultiConverter_Sync(&rfADC, XRFDC_ADC_TILE, &Config);
    if (syncStatus != XRFDC_MTS_OK) {
        warn("XRFdc_MultiConverter_Sync (groups) failed: %d", syncStatus);
        return;
    }
    printf("ADC synchronization complete:\n");
}
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Moderator
Moderator
109 Views
Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

OK @norume 

Let me have a go at reproducing it tomorrow. 

Keith 

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Moderator
Moderator
93 Views
Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Hi @norume 

I didn't manage to finish making this test case. I have the design built, I'll get it to run on my zcu111 tomorrow. 

I will update you again tomorrow. 

Keith 

 

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Moderator
Moderator
77 Views
Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

OK 

I didn't realise you were providing your own clock to the lmk. 

I tried to get this to work but there were some issues. 

When I took you lmx set up,my version of TicsPro warned me about some of the settings. I pressed on anyway and the lmx wouldn't lock for me. 

I'll spend some time again tomorrow. 

Keith

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Contributor
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Registered: ‎04-01-2015

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Yes, here are the settings.  I drive the RF clock section (J109) from J95 as shown the little diagram below.  The "FEVR" that I'm using as a reference to the LMK04208 jitter cleaner is based on the recovered clock from the GTY but you could just use an MMCM to produce a 125 MHz clock for your testing.

Screen Shot 2019-05-09 at 2.00.09 PM.pngBlock Diagram

FRF= 499.64 MHz

FEVR= FRF÷ 4 = 124.91 MHz

Fref_LMK04208= FEVR÷ 2 = 62.455 MHz

Fref_LMX2594= Fref_LMK04208= 62.455 MHz       (LMK04208 output 4)

FVCO= Fref_LMX2594× 128 = 7994.24 MHz

Fsamp= FVCO÷ 2 = FRF× 8 = 3997.120 MHz

FFPGA_REFLK_OUT_C= Fref_LMK04208= 62.455 MHz       (LMK04208 output 2)

FADC_AXI= FFPGA_REFLK_OUT_C× 8 = 499.64 MHz = Fsamp÷ 8

FSYSREF= Fref_LMK04208÷ 8 = 7.806875 MHz       (LMK04208 outputs 0 and 1)

The above values meet a number of constraints imposed by the hardware:

  • Fsamp ≤ 4 GHz
  • FFPGA_REFLK_OUT_C > 10 MHz (minimum reference to MMCM)
  • FSYSREF < 10 MHz
  • FADC_AXI synthesizable from FPGA_REFLK_OUT_C with MMCM PLL
  • FADC_AXI integer multiple of FSYSREF
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Moderator
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Registered: ‎04-18-2011

Re: RF ADC Multi-Tile Synchronization Intermittent Failure

Hi @norume 

I'll try to replicate this here. It might take some time. 

I don't have much experience with the Ethernet core. 

I guess I just need the recovered clock from the GTY?

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