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Visitor lennart_mle
Visitor
126 Views
Registered: ‎07-03-2018

RFSoC Interpreting ADC Data

Hi there,

I'm a little bit confused when looking at the tdata stream from my ADC. Here's a quick dump:

 0d3bfe49fdd3fefb00cc027f02c801a3
0d3bff8dffd000660113012d008fff4d
0d3b0025ff99ff5fffbafffcffd9ffd2
0d3bfe50fdeafe96ffdc010a014100ee
0d3bfc48fdb4003a025802f101f30004
0d3bfd3701190407046e029aff66fce1
0d3b024005b405eb02b4fe59fb4cfaea
0d3b078006b30256fd11f981f995fd54
0d3b07340191fb5cf7fdf8f2fdf703e3
0d3b005df98cf66ef8a1fef805780904
0d3bf7c2f50cf9020061073c0a340739
0d3bf4e3f9c8020d093f0b3c06a8fecd
0d3bfabc03f30ac00b8605d6fcfef5fa
0d3b05ef0c080b5e046afb16f496f48f

So we have a 128bit data stream due to running at 4GHz sampling rate and 500MHz Axi Clk. So far so good. 
According to the DS the 12Bits of the ADC are MSB aligned but instead I see how the 4 LSBs of every 16bit part of the 128 tdata toggles. Why is that? Furthermore the top 16bits of the tdata stream have the exact same value for every clk cycle. That doesn't seam right.

From the UG I would understand that I split the 128 bits in 16bit chunks and use the upper 12bits of each chunk as the ADC value. But looking at the above output this doesn't seam right.

Please correct my understanding of interpreting this data as it is obviously wrong.

Regards,

Lenn

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Moderator
Moderator
77 Views
Registered: ‎04-18-2011

Re: RFSoC Interpreting ADC Data

Table 57 of pg269 shows the digital data format. 

The axi stream is 16 bit 2s compliment. The table shows the shifted value to give the 12 bit accurate result

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Visitor lennart_mle
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Registered: ‎07-03-2018

Re: RFSoC Interpreting ADC Data

Hi Klumsde,

Which table are you referring to? Are you referring to PG269 Table 52?

Because of that table I expected the 4 LSBs of each 16bit chunk to be 0. Instead they have random values as we can see in the data of my first post.
So with the 128bit wide tdata vector I get the first line but I would expect something like the second line
0d3bfe49fdd3fefb00cc027f02c801a3
0d30fe40fdd0fef000c0027002c001a0

So is it correct that the 4LSBs of each 16bit chunk of the tdata axi stream vector are not zero but random values?

Furthermore I don't understand why the upper 16bit of my 128bit axi stream tdata vector always have the same value. This is definitely not because of my input signal!
Any suggestions what could cause that behavior?

Regards,
Lenn

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: RFSoC Interpreting ADC Data

The ADC is always outputting 16 bit conversion results.

Accuracy is guaranteed to 12-bits.

This is the table detailing the data formattble57.JPG

if the ADC is set up in Real in Real out mode like this:

  rfadc_real.JPG

 

rfadc_real_datastream.JPG

 

If I take what you gave me and convert the 16 bit hex number i see to 2's comp I see this

forum_adc_data_format.JPG

Is this what you are sending in? 

You always have the option to use RF analyzer to look at what is coming out of the ADC channel. 

 

Keith 

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Visitor lennart_mle
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Registered: ‎07-03-2018

Re: RFSoC Interpreting ADC Data

Hey Keith,

thanks for the detailed reply! We're currently using the ADC in I/Q Mode with the NCO running at 500MHz and no decimation (1x). The input is a 10MHz sine wave (not ideal, I know but all we can do at this moment). The samples I posted are from the real part only.
The wave you're plotting looks like what I've seen in Octave and is definitely not what we're sending in. What makes me most curious is that continuous 0x0d3b = 3387. I highly doubt that this is an actual sample, but what else could it be?

I probably should give the RF Analyzer a chance by now!

Last but not least: From what I'm seing in your Excel Spreadsheet, you're using the entire 16bit, while only the upper 12 should be valid right? For a rough plot it sure will be fine but for any kind of serious DSP I should through them away right? 

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: RFSoC Interpreting ADC Data

Hi

The sheet was something I used in the past for very quick validation of 16 bit ILA samples.

I didn't know it was iq data. 

Perhaps RF analyzer would be a good idea here you could capture and do an fft of what you are receiving via the GUI. This would also give you a chance to drive the ADC with the DAC output. 

I can't say what this fixed sample is just from the data you show. 

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