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Visitor bwtbirchp
Visitor
286 Views
Registered: ‎07-03-2019

RFSoC RF-DAC High Speed IQ

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Hi,

We're currently evaluating the RFSoC under simulation for use in a 'virtual-wire' type scenario, i.e.:

  • Analog I/Q data will be captured from a pair of ADCs at 3.5GS/s;
  • Piped through some logic;
  • Converted back to I/Q analog signals using a pair of DACs.

From our experiments so far, we've seen that there are two options for the DACs:

  • 'Bonded' mode - where two DACs are paired up to convert a single incoming interleaved AXI stream;
  • 'Independent' mode - where two DACs (still on the same tile) accept separate incoming AXI streams.

We're assuming that the 'bonded' mode ensures that the I and Q samples are aligned, whilst there is no such assertion for 'independent' mode.

However, the minimum interpolation mode in 'bonded' mode is 2x - meaning the effective maximum sample rate per DAC is only 3.277 GS/s (the maximum rate specified for the RF-DACs is 6.554 GS/s), which still falls short of the desired 3.5GS/s to match the ADCs. So aren't able to use 'bonded' mode.

This leaves us with the 'independent' mode. So firstly we plan to use locked clocks - a 220 MHz clock derived from the ADC will be used to drive the programmable logic, and to drive the DACs. However, we are concerned that this doesn't guarantee that the two independent AXI streams will be digested in lock step - especially since there is a CDC boundary within the hardened macro. We can't afford to get the two streams out of step.

So this leads to my questions:

  1. Is it possible to lower the interpolation mode to 1x in 'bonded' mode while still at 3.5 GS/s per DAC?
  2. If not, is the CDC within the DAC macro timed so that, with locked clocks, two DACs within the same tile are guaranteed to consume data at the same rate and in lock step?

Thanks,

Peter

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Xilinx Employee
Xilinx Employee
248 Views
Registered: ‎03-21-2008

Re: RFSoC RF-DAC High Speed IQ

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Hi Peter,

All channels within a tile are aligned, as long as the settings for the channels are the same (i.e. interpolation mode, FIFO width, etc) - so if you want full bandwidth IQ then you can simply use two 'real' or (independent) channels.

If you want to use IQ mixing within the tile to transform/shift the data centre frequency then you must use use the bonded mode you refer to, with interpolation by 2. Alternatively, you may do the mixing in the PL and use the 2 independent real channels as mentioned above.

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Xilinx Employee
Xilinx Employee
249 Views
Registered: ‎03-21-2008

Re: RFSoC RF-DAC High Speed IQ

Jump to solution

Hi Peter,

All channels within a tile are aligned, as long as the settings for the channels are the same (i.e. interpolation mode, FIFO width, etc) - so if you want full bandwidth IQ then you can simply use two 'real' or (independent) channels.

If you want to use IQ mixing within the tile to transform/shift the data centre frequency then you must use use the bonded mode you refer to, with interpolation by 2. Alternatively, you may do the mixing in the PL and use the 2 independent real channels as mentioned above.