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Registered: ‎07-18-2019

RfSoc ZCU111 DAC implementation with Baremetal


I have been trying to implement a DAC example in order to generate a sine waveform on DAC output.

The block diagram of my design is the following,


The usp_rf_data_converter was set as following:img1.png





The dds_compiler block is responsible for generating the sine waveform. I think that it correctly generates the sine waveform, since I am able to obtain the exepected signal and see it on ILA. However, when I connect an oscilloscope to usp_rf_data_converter I only see a constant voltage instead of a sine wave. DDS_compiler block was set as following:img4.png









 I used the baremetal library.

Project's code is in the following link: https://uapt33090-my.sharepoint.com/:f:/g/personal/marianaferreiraramos_ua_pt/Eq7cSZNwvmdLqxabanS1RYYBvI0hV9OYlTZdM4jhxlxAhw?e=OnY9Of.

If anyone has insight on this problem it would be greatly appreciated.

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2 Replies
Registered: ‎04-18-2011

Re: RfSoc ZCU111 DAC implementation with Baremetal

Hi @marianaferreiraramos 

In this case the first step I would do, if you haven't done it already is to boot the RF Analyzer Bitstream or the TRD for ZCU111, then try output this sine wave from the DAC you mention. If that works you know the hardware set up is good. 

Next I would use the PS to check the status of the IP. In particular the start up state machine that is part of the IP. If this is at it's end state the tile is running. Then we know the issue is somewhere before the DAC streaming input. I am guessing you see something coming out of the Streaming output you have connected to the ILA?

In this case as well, I don't think you can just connect the streaming data to 2 different IPs you need to put in the broadcaster to drive the ILA and the RFDC, if I remember correctly. Try this step as well.  

If the tile is not at it's end state you should be able to tell what is wrong by the state it is in. Usually the problem comes becuase you don't have the tile input clock running, so the state machine fails at the sample clock detect stage. 

In this case I would remind you that you have to program the clocks from the RF PLLs on the ZCU111. The way to do this is via the SW, there are 2 examples in the driver source on how to do this. Alternatively you could use the system controller to do this. 

Try the suggestions here and let us know how you get on. 



Don’t forget to reply, kudo, and accept as solution.
Community Manager
Community Manager
Registered: ‎08-30-2011

回复: RfSoc ZCU111 DAC implementation with Baremetal


Keith answered everything you can try on at the moment.

My two cents here is the clock needs to be programed if you start the board with JTAG. You can have a quick check on board of the clock leds. There are four leds on the left hand side of the board. It should stay on green after programming.

Don’t forget to reply, kudo, and accept as solution.