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Visitor escou64
Visitor
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Registered: ‎10-09-2018

Simple system for softcore

Hi everybody,

Please excuse my very simple questions (this is my first design for FPGA and I'm not an expert of DDR / AXI protocols) and thank you for your future answers.

I am currently working on a project where I have the RTL design of a processor that I am looking to implement on an Ultrascale+ ZCU104 board.
The first objective is very simple: generate reset and clock signals (100 MHz) as well as connect the design to the board's DDR4 memory. After looking at the different example projects available and several tests, here is below the Block Design I currently have and the associated errors:

system-view.png

messages-1.png

reset_system, clk_300mhz and ddr4_sdram are signals available on the board. S_AXI, reset and clk are the signals to be connected to the FPGA design. smartconnect_0 is to interface my design with the DDR4 MIG, and the two Processor System Reset are to synchronize reset with the clocks. Here I use the internal system of the DDR4 MIG to generate my clock as I have seen on other designs.

The main problem is clock management: I want my FPGA processor to run at 100MHz but this creates conflicts on the AXI bus it would seem, where a frequency of 266.5MHz seems mandatory.

Would anyone be able to explain to me where my mistake is (wrong approach? wrong scheme? maybe just values to change?)

Thank you again for your answers and have a nice day.

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