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UltraScale+ LPDDR3

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Visitor
Posts: 20
Registered: ‎11-01-2017
Accepted Solution

UltraScale+ LPDDR3

I use the XCZU3EG-1SFVC784I in my productio.VDDR uses 1.2V because we use lpddr3.Are the LPDDR3 circuits we designed to be correct?The circuit diagram is shown in PDF

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Moderator
Posts: 232
Registered: ‎06-30-2010

Re: UltraScale+ LPDDR3

the schematic looks good, please remember we don't do full schematic reviews that responsibility is on the customer. But looking at your connections they all look to be correct.
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Visitor
Posts: 20
Registered: ‎11-01-2017

Re: UltraScale+ LPDDR3

Visitor
Posts: 20
Registered: ‎11-01-2017

Re: UltraScale+ LPDDR3

Moderator
Posts: 232
Registered: ‎06-30-2010

Re: UltraScale+ LPDDR3

the schematic looks good, please remember we don't do full schematic reviews that responsibility is on the customer. But looking at your connections they all look to be correct.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Visitor
Posts: 20
Registered: ‎11-01-2017

Re: UltraScale+ LPDDR3

Thank you very much for your answer@jheslip
Moderator
Posts: 232
Registered: ‎06-30-2010

Re: UltraScale+ LPDDR3

no problem, when doing the layout please refer to the documentation for the skew/routing requirements. The main do is UG 583 for this.

If there are no further question on this thread please mark it as answered.
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Don’t forget to reply, kudo, and accept as solution.
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Visitor
Posts: 20
Registered: ‎11-01-2017

Re: UltraScale+ LPDDR3

Can the data line of the DDR be adjusted when the DDR chip is connected to the CPU?
Every 8 bit data adjustment,because PCB layout is more difficult.
Visitor
Posts: 20
Registered: ‎11-01-2017

Re: UltraScale+ LPDDR3

Moderator
Posts: 232
Registered: ‎06-30-2010

Re: UltraScale+ LPDDR3

sorry, i am not too sure what you mean. During the calibration there is adjustment / alignment done but there is limitation as to how much it can account for, this is why we have the guidelines.

In order to ensure a successful PCB they should all be followed.

What is the PCB difficulty that you are seeing?
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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Visitor
Posts: 20
Registered: ‎11-01-2017

Re: UltraScale+ LPDDR3

When layout, the DQ data line between DDR and CPU is disorderly.They cross too much between them.We want to make some adjustments. for example,Between DQ0-DQ7, we don't connect in order.We connect the DQ0 of DDR to the DQ2 of CPU.for the convenience of layout.@jheslip