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Observer bitstreamer
Observer
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Registered: ‎08-15-2018

Ultrascale+ Endpoint for PCI Express Root Port Model Location

Where did the testbench for the PCIe endpoint go? It's a PCIe setup as a root port.

It's referenced in PG195, Testbench->Root Port Model Test Bench for Endpoint.

I thought it was at the link below, it's not, it's also not in the reference design in 2018.2. Are testbenches for IP located in a common area?

I'd like to instantiate the Gen 3 PCIe with DMA and get a basic testbench running in linux. 

https://www.xilinx.com/support/answers/65751.html

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