03-16-2016 10:13 AM
In our setup, we need to provide 4x25 Gbps datastreams. By using the GTY wizard, the communication is set-up using a quad-PLL. By bypassing the TX buffers (buffer bypass option), one could expect that the phase alignement would solve most part of the lane by lane skew between the 4 streams.
Looking to the datastream, the skew between the 4 streams is almost resolved after setting the txbypass option. However, still some small variations in delay are observed.
One could think that certain delays are present due to routing delays of the clock (proposed by GTY application note). This however would yield a deterministic skew between the 4 lanes. However, upon reset, the skew between the lanes is not deterministic and can change over 10 to 20 ps.
Is there an extra option that can be used to obtain a deterministic skew (and even better, a skew which is even smaller) ?
Thanks in advance.
03-16-2016 01:55 PM - edited 03-16-2016 01:56 PM
Not at all sure you can get that degree of alignment. As each channel is independent, and will get received by its own clock and data recovery (CDR) why do you care?
03-16-2016 02:53 PM
We aim at multiplexing the signals generated by 4 GTY transmitters (25 Gbit each). For proper sampling of the 4 streams in our multiplexer, the 4 lanes should be aligned at the transmitter. However, the alignment performed by using the transmitter buffer bypass (hence, using the transmitter phase alignment proposed by p106 in "GTY Transceivers Advance Specification User Guide") is not deterministic. After reset of the transceiver block, the alignment changes from lane to lane with several picoseconds.
A small misalignment would not be harmfull (within 1 to 2 bits is tolerable) but the non determinstic part of the alignment is a severe problem in our setup.
The alignement at the RX is not an issue as reception is not used in our setup.
03-16-2016 07:46 PM
I'm going to guess that OIF CEI 3.1 applies to your application. (Google for OIF_CEI_03.1.pdf)
This standard covers 4 x 25Gb/s links using differential traces on printed circuit boards with connectors, e.g. a CFP2 or CFP4 or QSFP28 socket.
If I've interpreted it correctly, Section 3.2.8 indicates that your multiplexer design would need to tolerate up to +/- 1000 ps of skew between lanes. It makes no statement about the repeatability of the skew beause it would change when another optics module was plugged in.
This implies that the receiver (your multiplexer) needs to perform independent CDR for each channel, then do its own alignment using one of the (various) dynamic lane alignment techniques, rather than just using a fixed "line build-out" skew adjustment.
OTOH, that standard may not apply to your application. If so, please ignore this post!
03-17-2016 06:59 AM - edited 03-17-2016 06:59 AM
I am unaware of how to disable this behavior. I will ask.
03-17-2016 08:57 AM
I'm back. Each of the GTY have a programmable output phase adjustment with ~ 1 ps resolution. You need to talk to your local FAE or I/O specialist to learn how to use it. Not sure how you make use of this.
My thanks to the internal team for answering this for me,
03-17-2016 09:32 AM
Thank you. How can i come into contact with them?
03-17-2016 10:45 AM
Call your local Xilinx authorized distributor and request an IO or serdes expert to help you (field applications engineer). They should know how to access this capability to help you,