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Adventurer
Adventurer
1,274 Views
Registered: ‎03-27-2017

Ultrascale+ MMCM Error

Target Hardware: VCU118

 

I am trying to instantiate an MMCM to generate a variable clock (settings controlled dynamically through DRP and CDDC ports by VIO) from a reference clock source (100 MHz PCIe slot clock).

 

The DRP clock and VIO clock source is a default 156.25 MHz SI570 chip on the development board.

 

See below error statements and code.

 

Reported Error:

 

 

[Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: 
clk_in1_p
core_clock_mmcm/inst/clkin1_ibufds/IBUFCTRL_INST
clk_in1_n
core_clock_mmcm/inst/clkin1_ibufds/DIFFINBUF_INST
 ["mmcm_test/mmcm_test/mmcm_test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc":3]
[Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: 
clk_in1_p
core_clock_mmcm/inst/clkin1_ibufds/IBUFCTRL_INST
clk_in1_n
core_clock_mmcm/inst/clkin1_ibufds/DIFFINBUF_INST
 ["mmcm_test/mmcm_test/mmcm_test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc":4]
[Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: 
clk_in1_p
core_clock_mmcm/inst/clkin1_ibufds/IBUFCTRL_INST
clk_in1_n
core_clock_mmcm/inst/clkin1_ibufds/DIFFINBUF_INST
 ["mmcm_test/mmcm_test/mmcm_test.srcs/constrs_1/new/top_mmcm_ip_wiz.xdc":11]

Top File:

module top_mmcm_ip_wiz(
vio_clock_p_pin, vio_clock_n_pin, clock_out, clk_in1_p, clk_in1_n
);

input vio_clock_p_pin, vio_clock_n_pin;
input clk_in1_p, clk_in1_n;
output clock_out;

wire vio_clock;
wire locked_out, cddcdone_out;
wire cddcreq_in;
wire [6:0] daddr_in;
wire dclk_in, den_in, drdy_out, dwe_out;
wire [15:0] din_in, dout_out;
wire reset_in;

IBUFDS #(
    .DQS_BIAS("FALSE") // (FALSE, TRUE)
)
IBUFDS_inst (
    .O(vio_clock), // 1-bit output: Buffer output
    .I(vio_clock_p_pin), // 1-bit input: Diff_p buffer input (connect directly to top-level port)
    .IB(vio_clock_n_pin) // 1-bit input: Diff_n buffer input (connect directly to top-level port)
);

vio_0 VIO (
  .clk(vio_clock),                // input wire clk
  .probe_in0(dout_out),    // input wire [15 : 0] probe_in0
  .probe_in1(drdy_out),    // input wire [0 : 0] probe_in1
  .probe_in2(dwe_out),    // input wire [0 : 0] probe_in2
  .probe_in3(locked_out),    // input wire [0 : 0] probe_in3
  .probe_in4(cddcdone_out),    // input wire [0 : 0] probe_in4
  .probe_out0(daddr_in),  // output wire [6 : 0] probe_out0
  .probe_out1(den_in),  // output wire [0 : 0] probe_out1
  .probe_out2(din_in),  // output wire [15 : 0] probe_out2
  .probe_out3(reset_in),  // output wire [0 : 0] probe_out3
  .probe_out4(cddcreq_in)  // output wire [0 : 0] probe_out4
);

  clk_wiz_0 core_clock_mmcm
   (
    // Clock out ports
    .clk_out1(clock_out),     // output clk_out1
    // Dynamic reconfiguration ports
    .daddr(daddr_in), // input [6:0] daddr
    .dclk(vio_clock), // input dclk
    .den(den_in), // input den
    .din(din_in), // input [15:0] din
    .dout(dout_out), // output [15:0] dout
    .drdy(drdy_out), // output drdy
    .dwe(dwe_out), // output dwe
    // Status and control signals
    .reset(reset_in), // input reset
    .locked(locked_out),       // output locked
   .cddcdone(cddcdone_out),    // output cddcdone
   .cddcreq(cddcreq_in),     // input  cddcreq
   // Clock in ports
    .clk_in1_p(clk_in1_p),    // input clk_in1_p
    .clk_in1_n(clk_in1_n)
  );    // input clk_in1_n
    
endmodule

Constraints:

set_property PACKAGE_PIN AY14 [get_ports clock_out]
set_property PACKAGE_PIN AL9 [get_ports clk_in1_p]
set_property PACKAGE_PIN H32 [get_ports vio_clock_p_pin]

set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets vio_clock_BUFGCE]

 

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3 Replies
Adventurer
Adventurer
1,253 Views
Registered: ‎10-26-2017

Re: Ultrascale+ MMCM Error

Hi bfung,

 

Your input clock 'clk_in1_p' is LOC'ed to pin AL9, which is a transceiver MGT clock signal, specifically the PCIE clock.

 

You can't use an IBUFDS to buffer a transceiver MGT clock signal, you need to use the specific buffer for Ultrascale+  transceiver clocks which is IBUFDS_GTE4. Page 255 of UG974 (Ultrascale Libraries Guide) has instantiation templates in both VHDL and Verilog.

 

The 'O' output of IBUFDS_GTE4 ties to MGTREFCLK0 of GTY bank 225 (where you have it LOC'ed now). The 'ODIV2' output of IBUFDS_GTE4 can be a div-by-2 or an exact copy of the original clock. This signal should be tied to a BUFG and then that output can be used wherever you like in the fabric.

 

Let me know if this works

-Dan

Moderator
Moderator
1,192 Views
Registered: ‎06-30-2010

Re: Ultrascale+ MMCM Error

did the observation from @dancurry solve the issue, if so please mark it as the accepted solution.
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0 Kudos
Adventurer
Adventurer
1,179 Views
Registered: ‎03-27-2017

Re: Ultrascale+ MMCM Error

will do so when I get the chance to test - sorry for the delay.
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