01-15-2019 03:48 AM
Dear Xilinx Community,
I am using a Zynq-Ultrascale+ with VIVADO 2017.4 and I am having issues when dealing with IDELAYE3 and IDELAYCTRL primitives. My goal is to delay an input signal of about 10 ps so that the input signal and the output signal are 10 ps apart (I am aware that IDELAYE3 primitives inserts a default delay in excess to the 10 ps). I went through the UG571 userguide and find out that whenever an IDELAYE3 in TIME mode gets instantiated for its correct functionment also the IDELAYCTRL needs to be deployed. Both IDELAYE3 and IDELAYCTRL are supplied with the same 300MHz ref_clk signal, generated from a PLL, and a reset signal in compliance to the reset assertion/deassertion procedure described in the datasheet (I made sure everything behaves as described in the user guide).
With that being sad I'll get to the point: if I set 10 ps as TIME delay in the IDELAYE3 the Behavioral simulation returns me 8 ps of difference instead of 10 ps.
In the attached design (delayer.vhd) an input signal 'hit' (valid_hit) is fed to 4 parallel IDELAYE3: the 4 different IDELAYE3 have different TIMEs (in ps) as DELAY_VALUE so that each stage (parallel) adds 0,10,20,30 ps to the input signal. My problem is basically that when running the Behavioral simulation 10ps become 8ps, 20ps become 16ps and 30ps become 24ps.
Where am I mistaking?
Please see attached .vhd code 'delayer' and ISIM script (.txt)to force signals into simulation. PLL should be re-instantiated in case you may want to run the code. It's a simple PLL with in,out,reset and locked signals. Taking in 100MHz and giving out 300MHz.
Thanks in advance for your help,
01-15-2019 05:03 AM
I don't use simulation so much, but you might need to comply with this AR:
Also, 300-MHz is the absolute bottom of the range of acceptable IODELAYCTRL reference frequencies. I prefer to use a 350- or 400-MHz reference, which provides some margin from the floor.
Your reference clock does not need to go to the IODELAYs, since they're operating in FIXED mode. They just need to know the frequency of the reference that's being sent to the associated* IODELAYCTRL.
* That's interesting... IODELAYs are associated with a particular IODELAYCTRL by their placement. How are the underlying connections between them made, in simulation?
01-21-2019 01:19 AM
Dear Joe G.,
Thanks for your reply but I think I have found the solution in this other post linked below
If this post clears out the simulation misbehavior it remains unclear how to overcome the 'Critical Warnings' Vivado Generates after synthesis.
01-30-2019 12:51 AM - edited 01-30-2019 01:05 AM
Dear Xilinx Community,
I have an update to share on this post.
When using the code I posted in a real-life scenario, setting
IDELAYCTRL -- SIM DEVICE = ULTRASCALE
IDELAYE3 -- SIM DEVICE = ULTRASCALE_PLUS
with an REF_CLK frequency of 400MHz
I have tested with an oscilloscope the delay between two signals I fed into 2 different IDELAYE3 and the relative DELAY_VALUE between these two signal was always 0.8 times the original DELAY_VALUE I set into IDELAYE3 attributes.
For example if one IDELAYE3 had 0ps as DELAY_VALUE and the second one had 900 ps the time difference dt between the output signals was measured to be 720ps instead of 900ps : which is exactly 0.8 * 900 ps!!
(I of course made sure the paths of these two signals, before the oscilloscope, were equal in length and impedance)
The result I got is perfectly in line with the simulation values I was getting at first!!
How come IDELAYE3 for ULTRASCALE_PLUS has a 0.8 correction factor?
Please share your opinion on this,