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366 Views
Registered: ‎07-16-2019

Znyq Rfsoc ADC clock not present

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Hi I'm running a program on the FPGA to test the RF-ADC output but vivado cannot detect the ila. To check the clock I have flashed the FPGA with some logic to blink the LED with the clock (attached).

However, none of the LED's light up?

Is there another way to test the clock?

Is my test logic incorrect i.e. should I connect the ila clock straight to the free running adc clock with a IBUFDS?

How do i configure the clock chip (LMX2582RHA) on this board as the SPI pins are connected to the FPGA with no break out?

Thanks for your help in advance

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51 Views
Registered: ‎07-16-2019

Re: Znyq Rfsoc ADC clock not present

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Hi,

 

Thanks for your help, two days  ago I used the Cortex-R PS to run a C code program I wrote to program the clock chip using the SPI drivers. Now everything is working. Thanks

11 Replies
Contributor
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Registered: ‎08-27-2018

Re: Znyq Rfsoc ADC clock not present

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@michael.woodward,
Hi,
The clock cannot be tested with leds. Human eye can only detect flashes below 80 Hz. In that sense, the clock is unimaginably high frequency for the human eye to detect on leds. You can hook up an oscilloscope and check that clock or you could do a simulation. I'm not sure but I think ila should have a clock that is used by your design.

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Registered: ‎07-16-2019

Re: Znyq Rfsoc ADC clock not present

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Thanks for your reply but in the .vhd file above I have a process for clock division.

 

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Registered: ‎08-27-2018

Re: Znyq Rfsoc ADC clock not present

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@michael.woodward,
Hi,
The divided clock is still too high for you to see the leds blinking. Connect the pin to an oscilloscope. That is the easiest way. Or do a simulation.

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Moderator
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Registered: ‎04-18-2011

Re: Znyq Rfsoc ADC clock not present

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@michael.woodward I can see a bigger problem I think, the tile output clock is clocking the axi lite clock, I am not sure this will work because you need a clock on this to start the tile up. I suspect that the tile output clock(which is a divided version of the digital clock in the the tile) doesn't come up until after the tile has reached its end state. 

you could drop in the processor subsystem and boot it and use the pl output clock to clock the axi lite interface of the tile. 

In this case you would also be able to know that the tiles were started properly. 

 

Keith 

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231 Views
Registered: ‎07-16-2019

Re: Znyq Rfsoc ADC clock not present

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Hi,

Thanks for your reply. I did have suspicions of this so I changed my design to the diagram attached but forgot to update the design in this thread. I'm monitoring the locked outputs to test for the ADC clock as the clock pin is dedicated so vivado will not let my add an ILA to it. I'm finding the external clock into clock wizard 0 (100MHZ in, 57.5MHZ out) is locking. However, the other locks from the RF-ADC block in to clock wizard 1 is not locking. Also, when I use the RF-Analyzer tool I get the error shown in the right of the screenshot attached. I am correct to conclude that chip that generates the clock ADC needs to be configured? Unfortunately, I am using the custom board attached which does not break out the ADC clock to a header so it can't be scoped. Also, the SPI pins to the LMX2594 chip are not connected to bank 87 in the FPGA are not broken out. Therefore, are they GPIO pins on this board that these SPI pins can be mapped to so I can use the TI SPI USB module or is there an example design I can flash to the FPGA that will program this chip for me?

Thanks for any help in advance.

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Registered: ‎04-18-2011

Re: Znyq Rfsoc ADC clock not present

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Hi
There's no screenshot of the RF Analyzer error.
Can you please share it.
Again, I'd encourage you to drop in the processor block in and try to get the IP status, right now you can't be certain if the tile has reached its end state of its start up state machine or not..

From other threads you have posted you seem to be having problems getting a tile clock to the device, this is the first step to getting this up and running

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Registered: ‎07-16-2019

Re: Znyq Rfsoc ADC clock not present

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Hi,

Thanks for your reply. Not sure why the screen shot didn't attach, I'll edit this reply tommorrow and attach it. May I ask if you know any good resources that explain how to use the processor block to check the status? It might be worth mentioning that last week I connected the RF-ADC block with a JTAG-AXI bridge block and then used the TCL console to read the status register which came back as 0x0000. This to me suggests the block is not starting up (stuck at stage 0) which is why I think it is a clock issue. Therefore, I want to re-configure the clock generator chip. 

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Registered: ‎04-18-2011

Re: Znyq Rfsoc ADC clock not present

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I suspect the tile is getting no clock. How do you program the RF PLL on those boards?

 

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Registered: ‎07-16-2019

Re: Znyq Rfsoc ADC clock not present

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See screen shot of RF analyzer attached as promised. In reply to your last reply:

This is also my suspicion and the question I'm asking. Seems they have connected the SPI pins straight to the FPGA and not broken them out to a header. Therefore, the USB2ANY TI programming module cannot be used and it has to be programmed with the FPGA. Any thoughts on how to do this would be great. Unforntuanely there are no input pins connected to jumpers which I could connected the programing module to and then map to the SPI pins of the chip. Programming the chip through SPI with some c code on the MPSOC or a microblaze seems quite complicated.

RF Analyser.png
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Registered: ‎04-18-2011

Re: Znyq Rfsoc ADC clock not present

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is it connected to the PS of the Zynq. 

If so we could use the zynq PS to program it we could get it to program the clocks this way. 

It would take some work but it could work. 

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Registered: ‎07-16-2019

Re: Znyq Rfsoc ADC clock not present

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Hi,

 

Thanks for your help, two days  ago I used the Cortex-R PS to run a C code program I wrote to program the clock chip using the SPI drivers. Now everything is working. Thanks