UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer jcbrackett123
Observer
211 Views
Registered: ‎09-14-2009

Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

Hi

I have an OSERDESE3 (migrated from OSERDESE2) design that is giving me pulsewidth errors. 

    u_oled_oserdes : OSERDESE3
      generic map (
        DATA_WIDTH       => 8,
        ODDR_MODE        => "TRUE",
        OSERDES_D_BYPASS => "FALSE",
        OSERDES_T_BYPASS => "TRUE",
        SIM_DEVICE       => "ULTRASCALE_PLUS",
        SIM_VERSION      => 2.0)
      port map (
        OQ     => s_OLED_pin(i),
        T_OUT  => open,
        CLK    => Clk_In_4x,
        CLKDIV => Clk_In_1x,
        D(0)   => s_OLED_To_Ser_Byte(i)(7),
        D(1)   => s_OLED_To_Ser_Byte(i)(6),
        D(2)   => s_OLED_To_Ser_Byte(i)(5),
        D(3)   => s_OLED_To_Ser_Byte(i)(4),
        D(4)   => s_OLED_To_Ser_Byte(i)(3),
        D(5)   => s_OLED_To_Ser_Byte(i)(2),
        D(6)   => s_OLED_To_Ser_Byte(i)(1),
        D(7)   => s_OLED_To_Ser_Byte(i)(0),
        RST    => Reset_1x,
        T      => '0');

Clk_In_4x is 340.2 MHz and Clk_in_1x is 85.05MHz.  there is no reason for pulsewidth errors to occur, both clocks come from the same MMCM and are generated from a 216MHz clock.  The V7 design (OSERDESE2) used the same method and rates. 

timing report with errors

Check TypeCornerLib PinReference PinRequiredActualSlackLocationPin
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.50-0.11BITSLICE_RX_TX_X0Y47u_oled_sxga096/oled_serializers[1].u_oled_oserdes/CLKDIV
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.49-0.10BITSLICE_RX_TX_X0Y45u_oled_sxga096/oled_serializers[3].u_oled_oserdes/CLKDIV
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.49-0.10BITSLICE_RX_TX_X0Y43u_oled_sxga096/oled_serializers[4].u_oled_oserdes/CLKDIV
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.49-0.10BITSLICE_RX_TX_X0Y39u_oled_sxga096/oled_serializers[2].u_oled_oserdes/CLKDIV
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.47-0.08BITSLICE_RX_TX_X0Y41u_oled_sxga096/oled_serializers[0].u_oled_oserdes/CLKDIV

Why am i getting pulsewidth errors?

0 Kudos
1 Solution

Accepted Solutions
Community Manager
Community Manager
103 Views
Registered: ‎08-08-2007

Re: Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

Hi @jcbrackett123 

 

The skew requirement is a new requirement in UltraScale (was not previously in 7 Series).

If you are missing the skew requirement there are details of how you can try to workaround it  in this AR : https://www.xilinx.com/support/answers/67885.html

The first step is to use one MMCM output for both CLK and CLKDIV and use two BUFGCE_DIV with one to divide for the CLKDIV, this will remove the phase error from the MMCM in the timing, its roughly around 110ps so with the snippet below you are missing the skew by about 110ps so that may be enough to met the skew requirements.

If not there are other steps in the AR on setting constraints to improve the skew between the two clocks.

Sandy

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Tags (1)
7 Replies
Observer jcbrackett123
Observer
186 Views
Registered: ‎09-14-2009

Re: Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

To me it seems like vivado (2018.3) is treating the OSERDESE3 as SDR when it is set up to be DDR.  These signals also throw setup errors from the register to the oserdes.  It has errors going from 1x clock (85.05MHz called s_video_clock_4x_gen) to the 4x clock (340.2MHz called s_video_clock_16x_gen) on the oserdes

NameSlackLevelsRoutesHigh FanoutFromToTotal DelayLogic DelayNet DelayRequirementSource ClockDestination ClockExceptionClock Uncertainty
Path 327-0.40011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[1][2]/Cu_oled_sxga096/oled_serializers[1].u_oled_oserdes/D[5]0.660.130.522.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 328-0.40011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[1][6]/Cu_oled_sxga096/oled_serializers[1].u_oled_oserdes/D[1]0.610.140.472.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 329-0.38011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[2][6]/Cu_oled_sxga096/oled_serializers[2].u_oled_oserdes/D[1]0.610.130.472.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 330-0.37011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[1][7]/Cu_oled_sxga096/oled_serializers[1].u_oled_oserdes/D[0]0.610.130.472.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 331-0.37011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[3][6]/Cu_oled_sxga096/oled_serializers[3].u_oled_oserdes/D[1]0.610.130.472.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 332-0.37011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[4][3]/Cu_oled_sxga096/oled_serializers[4].u_oled_oserdes/D[4]0.590.130.452.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 333-0.37011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[4][6]/Cu_oled_sxga096/oled_serializers[4].u_oled_oserdes/D[1]0.600.130.472.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 334-0.35011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[3][3]/Cu_oled_sxga096/oled_serializers[3].u_oled_oserdes/D[4]0.600.130.472.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 335-0.35011u_oled_sxga096/s_OLED_To_Ser_Byte_reg[4][7]/Cu_oled_sxga096/oled_serializers[4].u_oled_oserdes/D[0]0.600.130.472.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
Path 336-0.34012u_oled_sxga096/s_OLED_To_Ser_Byte_reg[0][4]_replica/Cu_oled_sxga096/oled_serializers[0].u_oled_oserdes/D[1]0.620.140.482.94s_video_clk_4x_gens_video_clk_16x_gen 0.21
0 Kudos
Community Manager
Community Manager
139 Views
Registered: ‎08-08-2007

Re: Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

Hi @jcbrackett123 

 

The problem is this line in the code

   ODDR_MODE        => "TRUE",

 

As you are not trying to use the OSERDES as an ODDR the ODDR_MODE should be FALSE.

 

From UG571

ODDR.PNG

 

If you set the ODDR_MODE        => "FALSE", this should resolve your timing issues.

 

Sandy

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Observer jcbrackett123
Observer
133 Views
Registered: ‎09-14-2009

Re: Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

I am using the OSERDES as a ODDR.  I am serializing 8:1 which means you have to put it in ODDR mode.

0 Kudos
Community Manager
Community Manager
124 Views
Registered: ‎08-08-2007

Re: Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

Hi @jcbrackett123 

 

ODDR means 2:1.

As you are using 8:1 that is an OSERDES not an ODDR. In UltraScale all OSERDES are in double data rate there is no DATA_RATE attribute. 

You need to set the ODDR_MODE = FALSE unless you are trying to use the ODDRE1 primitive.

 

Sandy

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Observer jcbrackett123
Observer
112 Views
Registered: ‎09-14-2009

Re: Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

Thank you for the clarification.  However this does not fix the pulsewidth errors.  I have verified in the implemented design that the properties on the OSERDES components have ODDR_MODE = FALSE

NameValue
BELBITSLICE_COMPONENT_RX_TX.OSERDES
BOX_TYPEPRIMITIVE
CLASScell
DATA_WIDTH8
FILE_NAMEC:/projects/bino_fw/build/envgb_top/envgb_top.edif
INIT1'b0
IS_BEL_FIXEDfalse
IS_BLACKBOXfalse
IS_CLKDIV_INVERTED1'b0
IS_CLK_INVERTED1'b0
IS_DEBUGGABLEtrue
IS_LOC_FIXEDtrue
IS_MATCHEDtrue
IS_ORIG_CELLtrue
IS_PRIMITIVEtrue
IS_REUSEDfalse
IS_RST_INVERTED1'b0
IS_SEQUENTIALtrue
LINE_NUMBER502450
LOCBITSLICE_RX_TX_X0Y41
NAMEu_oled_sxga096/oled_serializers[0].u_oled_oserdes
ODDR_MODEFALSE
OSERDES_D_BYPASSFALSE
OSERDES_T_BYPASSTRUE
PARENTu_oled_sxga096
PRIMITIVE_COUNT1
PRIMITIVE_GROUPI/O
PRIMITIVE_LEVELLEAF
PRIMITIVE_SUBGROUPSERDES
PRIMITIVE_TYPEI/O.SERDES.OSERDESE3
REF_NAMEOSERDESE3
REUSE_STATUS 
SIM_DEVICEULTRASCALE_PLUS
SIM_VERSION2.00
SLR_INDEX0
STATUSFIXED

 

Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.50-0.11BITSLICE_RX_TX_X0Y47u_oled_sxga096/oled_serializers[1].u_oled_oserdes/CLKDIV   
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.49-0.10BITSLICE_RX_TX_X0Y45u_oled_sxga096/oled_serializers[3].u_oled_oserdes/CLKDIV   
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.49-0.10BITSLICE_RX_TX_X0Y43u_oled_sxga096/oled_serializers[4].u_oled_oserdes/CLKDIV   
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.49-0.10BITSLICE_RX_TX_X0Y39u_oled_sxga096/oled_serializers[2].u_oled_oserdes/CLKDIV   
Max SkewSlowOSERDESE3/CLKDIVOSERDESE3/CLK2.392.47-0.08BITSLICE_RX_TX_X0Y41u_oled_sxga096/oled_serializers[0].u_oled_oserdes/CLKDIV   
0 Kudos
Community Manager
Community Manager
104 Views
Registered: ‎08-08-2007

Re: Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

Hi @jcbrackett123 

 

The skew requirement is a new requirement in UltraScale (was not previously in 7 Series).

If you are missing the skew requirement there are details of how you can try to workaround it  in this AR : https://www.xilinx.com/support/answers/67885.html

The first step is to use one MMCM output for both CLK and CLKDIV and use two BUFGCE_DIV with one to divide for the CLKDIV, this will remove the phase error from the MMCM in the timing, its roughly around 110ps so with the snippet below you are missing the skew by about 110ps so that may be enough to met the skew requirements.

If not there are other steps in the AR on setting constraints to improve the skew between the two clocks.

Sandy

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Tags (1)
Observer jcbrackett123
Observer
88 Views
Registered: ‎09-14-2009

Re: Zync Ultrascale+ OSERESE3 Pulsewidth Timing Errors

Jump to solution

Sorry for the delay.  I had to try a couple different things AR# 67885 suggests in order to close the errors.  I am still work on locking down the timing so its consistant but what it suggested did work in the end.  Thanks for you're help.

0 Kudos