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Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

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Observer
Posts: 22
Registered: ‎10-06-2008
Accepted Solution

Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

On a Zynq Ultrascale+ board we're having difficulties in reading values of the VCC_PSPLL3 (AMS) register at 0xFFA5006C.

According to documentation (UG1085 v1.5 March 31, 2017), this register is described as the value of VCC_PSBATT voltage measurement. We're currently only reading 0x00000000 with and without a battery present on the board.

Unfortunately, we seem to be unable to find in the documentation how we can activate the monitoring on this register so that we would read this battery voltage.

Best regards,


Accepted Solutions
Xilinx Employee
Posts: 45
Registered: ‎04-18-2011

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

Hi Baxter, 

 

After speaking to engineering we think that this should indeed be present. 

I don't really know if there is a compelling use case to sample it other than to check if it is there.

 

There is a re-write planned for the TRM so we are planning to improve the description of these registers.

 

Can you try the following. 

 

Put the PS SYSMON into single channel mode. 

"The single-channel mode measures one sensor channel at a time. Write the channel number into the CONFIG_REG0 [mux_channel] bit field and select single-channel mode in the CONFIG_REG1 [sequence_mode] bit field.

The sensor channel numbers are listed in the sensor channel tables. All channels support long acquisition [ACQ] and the external channels support input sampling type [BU] functions, refer to the CONFIG_REG0 register.

Wait for the EOC interrupt and then read the associated measurement register.”"

 

The VCC_PSBATT channel number is 51 (decimal). [mux_channel likely needs the hex value]
The voltage is measured by the PS SYSMON unit and posted in AMS.VCC_PSPLL3.

 

Another alternative is to try add it to the low rate sequencer. 

VCC_PSBATT channel might be enabled in a sequence (low-rate loop, [sequence_mode] = 0010) by setting a bit in the private register SEQ_BASIC_MONITOR_CHANNEL0 [3] (address offset 0x01F4 (offset 0x07D in JTAG)).

 

can you try these and let me know if either one works?

 

 

View solution in original post


All Replies
Moderator
Posts: 8,401
Registered: ‎02-27-2008

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

b,

 

I do not believe this reads the battery voltage.

 

I do not see any connection to the PS XADC from the backup battery supply anywhere, in any document.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Observer
Posts: 22
Registered: ‎10-06-2008

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

The VCC_PSBATT is part of a register group described in 2 documents UG1085 and UG1087:AMS Module Register Summary UG1085 w mark paint.pngAMS Module Register Summary w mark paint.png

 

This Adam Taylor's chronicle also mentions the battery voltage register as part of a AMS Block accessible with the XSYSMON_AMS identifier.

 

We can successfully read others sysmon measurement accessible by the XSYSMON_PS and XSYSMON_PL identifier, but with XSYSMON_AMS it always returns 0x00000000.

 

An activation sequence or procedure specific to those registers seems to be missing.

 

Moderator
Posts: 8,401
Registered: ‎02-27-2008

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

I saw that,

 

I suspect it is in error.  I am asking design.  My reasoning is the level shifter required for this pin would be 1000X the load of the memory, depleting the battery if actually connected.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Xilinx Employee
Posts: 45
Registered: ‎04-18-2011

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

Hi Austin , Baxter,

 

I am taking a look at this. 

I also suspect it is an error. my understanding was the battery was only for when the device was powered off. 

Otherwise it would be powered off the vccaux rail... 

 

Keith 

Observer
Posts: 22
Registered: ‎10-06-2008

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

Our goal is to get the battery status and presence. I understand that it would be impossible to do it that way.

 

What about the others XSYSMON_AMS registers which also seems to return 0x00000000 ?

Xilinx Employee
Posts: 45
Registered: ‎04-18-2011

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

Hi Baxter, 

 

After speaking to engineering we think that this should indeed be present. 

I don't really know if there is a compelling use case to sample it other than to check if it is there.

 

There is a re-write planned for the TRM so we are planning to improve the description of these registers.

 

Can you try the following. 

 

Put the PS SYSMON into single channel mode. 

"The single-channel mode measures one sensor channel at a time. Write the channel number into the CONFIG_REG0 [mux_channel] bit field and select single-channel mode in the CONFIG_REG1 [sequence_mode] bit field.

The sensor channel numbers are listed in the sensor channel tables. All channels support long acquisition [ACQ] and the external channels support input sampling type [BU] functions, refer to the CONFIG_REG0 register.

Wait for the EOC interrupt and then read the associated measurement register.”"

 

The VCC_PSBATT channel number is 51 (decimal). [mux_channel likely needs the hex value]
The voltage is measured by the PS SYSMON unit and posted in AMS.VCC_PSPLL3.

 

Another alternative is to try add it to the low rate sequencer. 

VCC_PSBATT channel might be enabled in a sequence (low-rate loop, [sequence_mode] = 0010) by setting a bit in the private register SEQ_BASIC_MONITOR_CHANNEL0 [3] (address offset 0x01F4 (offset 0x07D in JTAG)).

 

can you try these and let me know if either one works?

 

 

Observer
Posts: 22
Registered: ‎10-06-2008

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

Thank you for your reply, I'm trying that right now.

Xilinx Employee
Posts: 45
Registered: ‎04-18-2011

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

OK, please update the Thread when you have some results.
Observer
Posts: 22
Registered: ‎10-06-2008

Re: Zynq Ultrascale+ - Unable to read VCC_PSBATT from sysmon

I'm able to read the VCC_PSBATT using the additional info given by Keith.

 

devmem2 0xFFA50904 w 0x3000 #Write PSSYSMON.CONFIG_REG1: Single channel mode
devmem2 0xFFA50900 w 0x0033 #Write PSSYSMON.CONFIG_REG0: mux_channel 51 for VCC_PSBATT
devmem2 0xFFA5006C #Read VCC_PSPLL3
--> 0x000087EE (~1.59V)

 

The documentation lacks 2 things here:

- The PSSYSMON.CONFIG_REG0: mux_channel bit field is missing in UG1087

- The sensor channel table, referencing VCC_PSBATT channel number 51, seems nowhere to be found

 

Thank you for your help