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how to estimate the CLB,register,cell FPGA utilization?

Posts: 142
Registered: ‎05-23-2017

how to estimate the CLB,register,cell FPGA utilization?

[ Edited ]


I am a little confuse about the difference between the CLB LUTs, CLB Registers (get following numbers from vivado).


On the Xilinx websites, we could see the resource is calculated by "system logic cell"




What is the relation between these three guys (system logic cell,CLB LUTs and CLB Registers )?


 Any hint will be appreciated!

Posts: 1,779
Registered: ‎06-24-2013

Re: how to estimate the CLB,register,cell FPGA utilization?

Hey @mathmaxsean,


If you look at UG474, specifically the diagrams in chapter 2, you can see that there are Slices which consist of quite a number of different elements.


One important part in each Logic Slice (SliceL and SliceM) are the Lookup Tables (LUTs) which basically take the function of gates (or complex ensembles of gates). Those are the LUTs.


Another part are the Flip Flops (FFs) which basically work as Registers to synchronize logic functions with a clock. Those are the Registers.


So a Logic Slice contains a number of LUTs (4/8) and Registers (8) as well as some other logic (Carry, Muxes, Gates).


Hope this clarifies,


-------------- Yes, I do this for fun!
Xilinx Employee
Posts: 9,292
Registered: ‎02-27-2008

Re: how to estimate the CLB,register,cell FPGA utilization?



Now that 'hp' has explained it, why do you care what the utilization is?


Generally, if your verilog or VHDL source synthesizes, functions properly, and meets timing, you are finished.  If your design runs out of resources (part is too small), one uses a larger part, or changes one's source code to reduce resource usage by examining the RTL schematics, and understanding what is using resource, and modifying it.


I a just curious why you care about the fine underlying details.

Austin Lesea
Principal Engineer
Xilinx San Jose
Posts: 97
Registered: ‎05-21-2015

Re: how to estimate the CLB,register,cell FPGA utilization?

Some time ago, I tried to summarize the information from UG474 into something that was more easily understood when it came to resource counting and estimation.  I didn't get all of the details quite right, so I may come back and update this, but the concept is pretty close.  In particular, I treated every flip-flop as though it had a constant CE line and no reset line.  Still, I think the blog article is still useful for estimating the resource usage of any particular algorithm.  (You can read about it here ...)


As to the question of why should one care, I offer this answer: If I wish to build a core that can be used by anyone, the LUT usage of that core IP is a "price" they will have to pay for that core in addition to any cost I might levy.  As others shop for such cores, they will look for the one that leaves them with the most LUTs left over for any other logic they would like to implement.



Posts: 2,663
Registered: ‎04-26-2015

Re: how to estimate the CLB,register,cell FPGA utilization?

@dgisselq That's a really interesting way of looking at it (including resource usage in the "price"). It provides a really neat way of trading off options like HLS vs HDL - HLS is much cheaper to purchase (because it almost invariably takes far less time to develop an algorithm in HLS) but the flip-side is that the resource cost is (probably) much higher.