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Newbie oleg.abr95
Newbie
46 Views
Registered: ‎11-20-2018

timing model for ddr4 batch simulation

Hi,

I have a problem while running the ddr4 batch simulation in hyperlynx.

I place the timing model of the ultrascale+ zynq ( I use the XCZU17EG-L1…)  as input.

The timing model of the ultrascale contains the minimal( 4v/nsec) and maximal(9v/nsec) slew rate among other parameters.

The mask hight is 136mV .

The dq read simulation pass successfully .

The dq write simulation of some dq signals fails because of the slew rate.

Can I please get an explanation why the slew rates are different in Xilinx an micron component?

What are the correct slew rate values for 2133Mbps and 2400Mbps data rate? And how can I derive the possible minimal and maximal slew rate by myself?

is there any additional parameters in the timing file that are different for 2400 and 2133Mbps data rate?

 

Thank you for your assistance.

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